1.1.3. DDR, DDR2, and DDR3 SDRAM Command and Address Signals
For DDR, DDR2, and DDR3, the CS#, RAS#, CAS#, WE#, CKE, and ODT pins are SDRAM command and control pins. For DDR3 SDRAM, certain topologies such as RDIMM and LRDIMM include RESET#, PAR_IN (1.5V LVCMOS I/O standard), and ERR_OUT# (SSTL-15 I/O standard).
The DDR2 SDRAM command and address inputs do not have a symmetrical setup and hold time requirement with respect to the SDRAM clocks, CK, and CK#.
For Intel® SDRAM high-performance controllers in Stratix III and Stratix IV devices, the command and address clock is a dedicated PLL clock output whose phase can be adjusted to meet the setup and hold requirements of the memory clock. The command and address clock is also typically half-rate, although a full-rate implementation can also be created. The command and address pins use the DDIO output circuitry to launch commands from either the rising or falling edges of the clock. The chip select CS#, clock enable CKE, and ODT pins are only enabled for one memory clock cycle and can be launched from either the rising or falling edge of the command and address clock signal. The address and other command pins are enabled for two memory clock cycles and can also be launched from either the rising or falling edge of the command and address clock signal.
In Arria II GX devices, the command and address clock is either shared with the write_clk_2x or the mem_clk_2x clock.
Did you find the information on this page useful?