External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents
Give Feedback Measuring Eye Reduction for Address/Command, DQ, and DQS Setup and Hold Time

This topic describes how to measure eye reduction for address/command, DQ, and DQS.

Channel signal integrity is a measure of the distortion of the eye due to intersymbol interference or crosstalk or other effects. Typically, when going from a single-rank configuration to a multi-rank configuration there is an increase in the channel loss due to reflections caused by multiple stubs. Although the Quartus Prime timing model includes some channel uncertainty, you must perform your own channel signal integrity simulations and enter the additional channel uncertainty, as compared to the reference eye, into the parameter editor.

For details about measuring channel signal integrity, refer to Measuring Channel Signal Integrity, on the Intel® FPGA Wiki page.