External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents

5.3.4. RLDRAM 3 Termination Schemes

The following table lists the recommended termination schemes for major CIO RLDRAM 3 memory interface signals. These signals include data (DQ), data mask (DM), clocks (CK, CK#, DK, DK#, QK, and QK#), address, bank address, and command (WE#, REF#, and CS#).
Table 43.  RLDRAM 3 Termination Recommendations for Arria V GZ and Stratix V Devices 
Signal Type Memory End Termination Option in the Chip (ODT) Recommended On-Board Terminations
Data Read (DQ, QK) 40, 60 (series) None
Data Write (DQ, DM, DK) 40, 60, 120 (parallel) None
Address/Bank Address/ Command (WE#, REF#, CS#) (1) (2) (3) None 50-ohm Parallel to Vtt
CK/CK# None 100 ohm Differential

Notes to Table:

  1. For width expansion configuration, the address and control signals are routed to 2 devices. Recommended termination is 50-ohm parallel to VTT at the trace split of a balanced T or Y routing topology. Use a clamshell placement of the two RLDRAM 3 components to achieve minimal stub delays and optimum signal integrity. Clamshell placement is when two devices overlay each other by being placed on opposite sides of the PCB.
  2. The UniPHY default IP setting for this output is Max Current. A Class I 50-ohm output with calibration output is typically optimal in single load topologies.
  3. Intel recommends that you use a 50-ohm parallel termination to VTT if your design meets the power sequencing requirements of the RLDRAM 3 component. Refer to the RLDRAM 3 data sheet for further information.
  4. QVLD is not used in the RLDRAM 3 UniPHY Intel FPGA IP implementations.
  5. For information on the I/O standards and on-chip termination (OCT) resistance values supported for RLDRAM 3, refer to the I/O Features chapter of the appropriate device handbook.

Intel recommends that you simulate your specific design for your system to ensure good signal integrity.