External Memory Interface Handbook Volume 2: Design Guidelines

ID 683385
Date 5/08/2017
Document Table of Contents Using Example Designs

When you generate your IP, you can instruct the system to produce an example design consisting of an external memory interface IP of your configuration, together with a traffic generator.

For synthesis, the example design includes a project for which you can specify pin locations and a target device, compile in the Quartus Prime software, verify timing closure, and test on your board using the programming file generated by the Quartus Prime assembler. For simulation, the example design includes an example memory model with which you can run simulation and evaluate the result.

For a UniPHY-based external memory interface, click Example Design in the parameter editor, or enable Generate Example Design. The system produces an example design for synthesis in the example_project directory, and generation scripts for simulation in the simulation directory. To generate the complete example design for RTL simulation, follow the instructions in the readme.txt file in the simulation directory.

For Arria 10 External Memory Interface IP, click Example Design in the parameter editor. The system produces generation scripts in the directory path that you specify. To create a complete example design for synthesis or RTL simulation, follow the instructions in the generated <variation_name>/altera_emif_arch_nf_140/<synth|sim>/<variation_name>_altera_emif_arch_nf_140_<unique ID>_readme.txt file.

To compile an example design, open the .qpf file for the project and follow the standard design flow, including constraining the design prior to full compilation. If necessary, change the example project device to match the device in your project.

For more information about example designs, refer to Functional Description—Example Top Level project in Volume 3 of the External Memory Interface Handbook. For more information about simulating an example design, refer to Simulating the Example Design in the Simulating Memory IP chapter.

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