External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

7.3.3. Parameterizing Memory Controllers

This section describes the parameters you can set for various UniPHY-based memory controllers.

Parameterizing Memory Controllers with UniPHY IP

The Parameter Settings page in the parameter editor allows you to parameterize the following settings for the LPDDR2, DDR2, DDR3 SDRAM, QDR II, QDR II+ SRAM, RLDRAM II, and RLDRAM 3 memory controllers with the UniPHY IP:

  • PHY Settings
  • Memory Parameters
  • Memory Timing
  • Board Settings
  • Controller Settings
  • Diagnostics

The messages window at the bottom of the parameter editor displays information about the memory interface, warnings, and errors if you are trying to create something that is not supported.

Enabling the Hard Memory Interface

For Arria V and Cyclone V devices, enable the hard memory interface by turning on Interface Type > Enable Hard Memory Interface in the parameter editor. The hard memory interface uses the hard memory controller and hard memory PHY blocks in the Arria V and Cyclone V devices.

The half-rate bridge option is available only as an SOPC Builder component, Avalon-MM DDR Memory Half-Rate Bridge, for use in a Qsys project.

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