External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents
Give Feedback

5.4. PCB Layout Guidelines

Intel recommends that you create your project in the Quartus® Prime software with a fully implemented RLDRAM II Controller with UniPHY Intel FPGA IP interface, or RLDRAM 3 UniPHY Intel FPGA IP, and observe the interface timing margins to determine the actual margins for your design.

Although the recommendations in this chapter are based on simulations, you can apply the same general principles when determining the best termination scheme, drive strength setting, and loading style to any board designs. Intel recommends that you perform simulations, either using IBIS or HSPICE models, to determine the quality of signal integrity on your designs, and that you get accurate time base skew numbers when you simulate your specific implementation.

  1. The following layout guidelines include several +/- length-based rules. These length‑based guidelines are for first order timing approximations if you cannot simulate the actual delay characteristics of your PCB implementation. They do not include any margin for crosstalk.
  2. To reliably close timing to and from the periphery of the device, signals to and from the periphery should be registered before any further logic is connected.