External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents
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3.3. Dual-Slot Unbuffered DDR3 SDRAM

The following topics detail the system implementation of a dual slot unbuffered DDR3 SDRAM interface, operating at up to 400 MHz and 800 Mbps data rates.

The following figure shows a typical DQS, DQ, and DM, and address and command signal topology for a dual-DIMM interface configuration, using the ODT feature of the DDR3 SDRAM components combined with the dynamic OCT features available in Stratix III and Stratix IV devices.

Figure 40. Multi DIMM DDR3 DQS, DQ, and DM, and Address and Command Termination Topology

In the above figure, observe the following points:

  • Board trace A = 1.9 to 4.5 inches (48 to 115 mm)
  • Board trace B = 0.425 inches (10.795 mm)
  • This topology to both DIMMs is accurate for DQS, DQ, and DM, and address and command signals
  • This topology is not correct for CLK and CLK# and control group signals (CS#, CKE, and ODT), which are always point-to-point single rank only.