External Memory Interface Handbook Volume 2: Design Guidelines

ID 683385
Date 5/08/2017
Document Table of Contents

12.1. Core Logic and User Interface Data Rate

The clocking operation in the PHY consists of the following two domains:
  • PHY-memory domain—the PHY interfaces with the external memory device and is always at full-rate.
  • PHY-AFI domain—the PHY interfaces with the memory controller and can either be at full, half or quarter rate of the memory clock depending on your choice of controller and PHY.

For the memory controller to operate at full, half and quarter data rate, the UniPHY IP supports full, half and quarter data rate. The data rate defines the ratio between the frequency of the Altera PHY Interface (AFI) clock and the frequency of the memory device clock.

the following table compares the clock cycles, data bus width and address/command bus width between the full, half, and quarter-rate designs.

Table 504.  Ratio between Clock Cycles, Data Bus Width, and Address/Command Bus Width

Data Rate

Controller Clock Cycles

Bus Width

AFI Data

AFI Address/Command













In general, full-rate designs require smaller data and address/command bus width. However, because the core logic runs at a high frequency, full rate designs might have difficulty in closing timing. Consequently, for high frequency memory interface designs, Intel® recommends that you use half-rate or quarter-rate UniPHY IP and controllers.

DDR3 SDRAM interfaces can run at much higher frequencies than DDR, DDR2 SDRAM, QDRII, QDRII+ SRAM, and RLDRAM II interfaces. For this reason, Altera High-Performance Controller II and UniPHY IPs do not support full rate designs using the DDR3 SDRAM interface. However, the DDR3 hard controller in Arria®  V devices supports only full rate. Quarter-rate design support is for DDR3 SDRAM interfaces targeting frequencies higher than 667 MHz.

Although it is easier to close timing for half-rate and quarter-rate designs due to the lower frequency required on the core logic, full-rate interfaces offer better efficiency for low burst-length designs. This is because of 1T addressing mode where the address and command signals are asserted for one memory clock cycle. Typically half-rate and quarter-rate designs operate in 2T and 4T mode, respectively, in which the address and command signals in 2T and 4T mode must be asserted for two and four memory clock cycles, respectively. To improve efficiency, the controller can operate in Quasi-1T half‑rate and Quasi-2T quarter-rate modes. In Quasi-1T half-rate mode, two commands are issued to the memory on two memory clock cycles. In Quasi-2T quarter-rate mode, two commands are issued to the memory on four memory clock cycles. The controller is constrained to issue a row command on the first clock phase and a column command on the second clock phase, or vice versa. Row commands include activate and precharge commands; column commands include read and write commands.

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