External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents
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2.7.3. Address and Command Deskew

Deskew address and command delays as follows:
  1. Select the FPGA Address/Command Package Skews Deskewed on Board checkbox on the Board Settings tab of the parameter editor.
  2. Generate your IP.
  3. Instantiate your IP in the project.
  4. Run Analysis and Synthesis in the Quartus Prime software.
  5. Run the <core_name>_p0_pin_assignment.tcl script.
  6. Compile your design.
  7. Refer to the All Package Pins compilation report, or find the pin delays displayed in the <core_name>.pin file.