External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
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9.9.8. Read Resynchronization and Write Leveling Timing (for SDRAM Only)

These timing paths apply only to Arria II GX, Stratix III, and Stratix IV devices, and are implemented using calibrated clock signals driving dedicated IOE registers. Therefore, no timing optimization is possible for these paths, and positive timing margin is expected for interfaces running at or below the FPGA data sheet specifications.

Ensure that you specify the correct memory device timing parameters (tDQSCK, tDSS, tDSH) and board skew (tEXT) in the DDR2 and DDR3 SDRAM Controllers with UniPHY parameter editor.