External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents
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1.6. Other FPGA Resources

The Intel® FPGA memory interface IP uses FPGA fabric, including registers and the Memory Block to implement the memory interface.

For resource utilization examples to ensure that you can fit your other modules in the device, refer to the “Resource Utilization” section in the Introduction to UniPHY IP chapter of the External Memory Interface Handbook.

One OCT calibration block is used if you are using the FPGA OCT feature in the memory interface.The OCT calibration block uses two pins (RUP and RDN), or single pin (RZQ) (“OCT Support for Arria II GX, Arria II GZ, Arria V, Arria V GZ, Cyclone V, Stratix III, Stratix IV, and Stratix V Devices”). You can select any of the available OCT calibration block as you do not need to place this block in the same bank or device side of your memory interface. The only requirement is that the I/O bank where you place the OCT calibration block uses the same VCCIO voltage as the memory interface. You can share multiple memory interfaces with the same OCT calibration block if the VCCIO voltage is the same.