External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

1.4.3.3. Interfacing with RLDRAM II and RLDRAM 3 ×36 CIO Devices

This topic describes interfacing with RLDRAM II and RLDRAM 3 x36 CIO devices.

RLDRAM II devices have the following pins:

  • 4 pins for QK/QK# signals
  • 36 DQ pins (in x16/x18 DQS group)
  • 4 pins for DK/DK# signals
  • 1 DM pins
  • 46 pins total (47 if you have a QVLD)

In the FPGA, you use two ×16/×18 DQS groups totaling 48 pins: 4 for the read clocks and 36 for the read data. Configure each ×16/×18 DQS group to have:

  • Two QK/QK# pins occupying the DQS/DQSn pins
  • Pick two DQ pins in the ×16/×18 DQS groups that are DQS and DQSn pins in the ×4 or ×8/×9 DQS groups for the DK and DK# pins
  • 18 DQ pins occupying the DQ pins
  • There are two DQ pins leftover that you can use for QVLD or DM pins. Put the DM pin in the group associated with DK[1] and the QVLD pin in the group associated with DK[0].
  • Check that DM is associated with DK[1] for your chosen memory component.

RLDRAM 3 devices have the following pins:

  • 8 pins for QK/QK# signals
  • 36 DQ pins (in x8/x9 DQS group)
  • 4 pins for DK/DK# signals
  • 2 DM pins
  • 48 pins total (49 if you have a QVLD)

In the FPGA, you use four ×8/×9 DQS groups.

In addition, observe the following placement rules for RLDRAM 3 interfaces:

For ×18 devices:

  • Use two ×8/×9 DQS groups. Assign the QK/QK# pins and the DQ pins of the same read group to the same DQS group.
  • DQ, DM, and DK/DK# pins belonging to the same write group should be assigned to the same I/O sub-bank, for timing closure.
  • Whenever possible, assign CK/CK# pins to the same I/O sub-bank as the DK/DK# pins, to improve tCKDK timing.

For ×36 devices:

  • Use four ×8/×9 DQS groups. Assign the QK/QK# pins and the DQ pins of the same read group to the same DQS group.
  • DQ, DM, and DK/DK# pins belonging to the same write group should be assigned to the same I/O sub-bank, for timing closure.
  • Whenever possible, assign CK/CK# pins to the same I/O sub-bank as the DK/DK# pins, to improve tCKDK timing.

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