External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

7.6. Document Revision History

Date Version Changes
May 2017 2017.05.08
  • Added Stratix 10 External Memory Interface IP section.
  • Rebranded as Intel.
October 2016 2016.10.31
  • Updated Generated Directory Structure and Key Files for Example Simulation Designs and Generated Directory Structure and Key Files for Example Synthesis Designs tables.
  • Removed Parameterizing Arria 10 External Memory Interface IP section.
  • Added protocol-specific parameter sections for Arria 10 EMIF IP.
  • Added Equations for Arria 10 EMIF IP Board Skew Parameters section.
May 2016 2016.05.02
  • Modified window duration in descriptions of tDQSCK Delta Medium and tDQSCK Delta Long in the Parameter Descriptions table in Memory Timing Parameters for DDR2, DDR3, and LPDDR2 SDRAM for UniPHY IP.
  • Modified description of Enable the Efficiency Monitor and Protocol Checker on the Controller Avalon Interface in the Simulation Options table in Diagnostics for UniPHY IP.
  • Removed cal_debug_burstcount from Interface: cal_debug_avalon_slave table in Qsys Interfaces.
  • Modified Direction information for entries in Interface: cal_debug_out_avalon_master table in Qsys Interfaces.
  • Removed two rows from the Generated Directory Structure and Key Files for Simulation table in Generated Files for Arria 10 External Memory Interface IP.
  • Replaced Generated Directory Structure and Key Files for Example Designs table with Generated Directory Structure and Key Files for Example Simulation Designs and Generated Directory Structure and Key Files for Example Synthesis Designs tables in Generated Files for Arria 10 External Memory Interface IP.
  • Added entry for Slew rate to Group: I/O / Address/Command and Group: I/O / Memory Clock tables in I/O Parameters for Arria 10 EMIF IP.
  • Modified description of DDR3 LRDIMM additional control words entry in Group: Memory Topology / Mode Register Settings table in Memory Topology Parameters for Arria 10 EMIF IP.
  • Modified supported protocol information for Enable Error Detection and Correction Logic and Enable Auto Error Correction entries in Group: Controller / Configuration, Status and Error Handling table in Controller Parameters for Arria 10 EMIF IP.
  • Minor change to description of Calibration mode in Group: Diagnostic / Simulation Options table in Diagnostic Parameters for Arria 10 EMIF IP.
  • Added QDR-IV to supported protocols for Skip VREF calibration in Group: Diagnostic / Calibration Debug Options table in Diagnostic Parameters for Arria 10 EMIF IP.
  • Added Calibration address 0, Calibration address 1, and Enable automatic calibration after reset to Group: Diagnostic / Calibration Debug Options table in Diagnostic Parameters for Arria 10 EMIF IP.
  • Added Group: Diagnostic / Traffic Generator table to Diagnostic Parameters for Arria 10 EMIF IP. Moved some entries from Group: Diagnostic / Example Design table to new Group: Diagnostic / Traffic Generator table.
November 2015 2015.11.02
  • Added note to descriptions of Minimum delay difference between CK and DQS and Maximum delay difference between CK and DQS in Board Skew parameters for LPDDR2/DDR2/DDR3 SDRAM.
  • Added text to description of Maximum skew between DQS groups in Board Skew parameters for LPDDR2/DDR2/DDR3 SDRAM.
  • Changed description of emif_usr_clk in the Interface: emif_usr_clk_clock_source table in Qsys Interfaces.
  • Changed description of emif_usr_reset_n in the Interface: emif_usr_reset_reset_source table in Qsys Interfaces.
  • Added Interface: emif_usr_clk_sec_clock_source and Interface: emif_usr_reset_sec_reset_source tables in Qsys Interfaces.
  • Added several options to the Simulation Options, Calibration Debug Options, and Example Design tables in Diagnostic Parameters for Arria 10 EMIF IP.
  • Changed instances of Quartus II to Quartus Prime.
  • Added LPDDR3
  • Removed Use address parity bit parameter for QDR IV
  • Removed following DDR4 parameters:
    • Write CRC enable
    • DDR4 geardown mode
    • Per-DRAM addressability
    • Temperature sensor readout
    • Write CMD latency for CRC/DM enable
    • MPR read format
    • CS to Addr/CMD Latency
    • Enable DM pins
    • Addr/CMD persistent error
    • Write DBI
    • Read DBI
  • Removed group board timing/slew rates table
  • Removed Maximum system skew within QK group parameters for RLDRAM 3
  • Removed Maximum system skew within Q group and Maximum skew within D group parameters
May 2015 2015.05.04 Added information to the Description column for the cal_debug_avalon_slave, cal_debug_clk_clock_sink, and cal_debug_out_reset_reset_source tables in the Qsys Interfaces topic.
December 2014 2014.12.15
  • Added MAX 10 device support to the PHY Parameters table in PHY Settings for UniPHY IP
  • Changed Memory Parameters for LPDDR2, DDR2, and DDR3 SDRAM table to accommodate MAX 10 devices.
  • Added Enable Deep Power-Down Controls parameter to Controller Settings table in Controller Settings for UniPHY IP section.
  • Arria 10 External Memory Interface IP section:
    • Removed references to Arria 10 devices from Board Settings topic in UniPHY-Based External Memory Interface IP section. Added new Board Timing topic.
    • Added QDR IV support to tables in Qsys Interfaces section.
    • Removed afi_c from afi_conduit_end table and mem_c from mem_conduit_end table.
    • Changed description of global_reset_n signal in the Interface: global_reset_reset_sink table.
    • Added Board Timing section and subtopics.
  • Changed Memory Initialization Options for DDR3 table to accommodate MAX 10 devices.
  • Replaced Parameter Descriptions table in Memory Timing Parameters for DDR2, DDR3, and LPDDR2 SDRAM for UniPHY IP section with new table including LPDDR2.
  • Removed General Settings for Arria 10 EMIF IP section.
  • Parameterizing Arria 10 External Memory Interface IP section:
    • Added DDR4 support to tables.
    • Changed descriptions of RDIMM/LRDIMM control words and LRDIMM additional control words in Group: Memory Topology / Mode Register Settings table.
    • Removed Chip ID Width from Group: Memory Topology / Topology table.
    • Added entry for Instantiate two controllers sharing a Ping Pong PHY, and expanded description of Configuration, in the Group: General / Interface table.
    • Changed Total interface width entry to DQ width and changed Place ALERT# pin to ALERT# pin placement in Group: Memory Topology / Topology table.
August 2014 2014.08.15
  • Added notes about Arria 10 EMIF IP to beginning of chapter.
  • Added IP Catalog to Design Flows figure.
  • Replaced MegaWizard Plug-In Manager Flow with IP Catalog Design Flow.
  • Revised Specify Parameters for the Qsys Flow and Completing the Qsys System sections.
  • Added information to description of mem_doff_n in QDR II and QDR II+ SRAM Controller with UniPHY Interfaces table.
  • Reorganized into separate sections for UniPHY-Based External Memory Interfaces and Arria 10 External Memory Interface IP.
  • Replaced the following sections with the new Arria 10 EMIF IP Interfaces section:
    • DDR3 Controller with Arria 10 EMIF Interfaces
    • LPDDR2 SDRAM Controller with Arria 10 EMIF Interfaces
    • QDR II/II+ Controller with Arria 10 EMIF Interfaces
    • RLDRAM II Controller with Arria 10 EMIF Interfaces
    • RLDRAM 3 Controller with Arria 10 EMIF Interfaces
  • Changed name of Generated Files for Memory Controllers with Arria 10 EMIF IP section to Generated Files for Arria 10 External Memory Interface IP, and revised content.
  • Revised content of General Settings for Arria 10 EMIF IP section.
  • Added Parameterizing Arria 10 External Memory Interface IP section.
  • Revised content of Memory Topology for LPDDR2, DDR3 and DDR4 SDRAM for Arria 10 EMIF IP section.
  • Added Memory Parameters for QDR IV for Arria 10 EMIF IP section.
  • Revised Memory Parameters for RLDRAM 3 for Arria 10 EMIF IP section.
  • Added slew rate information for QDR II, QDR II+, and QDR II+ Xtreme to table in Slew Rates for Arria 10 EMIF IP section.
  • Revised ISI Parameters table in Intersymbol Interference Channel Signal Integrity for UniPHY IP section.
  • Revised description of fly-by topology for UDIMMs in Board Skews for UniPHY IP section.
  • Added MAX 10 to Simulation Options table in Diagnostics for UniPHY IP section.
  • Added note to descriptions of Minimum delay difference between CK and DQS and Maximum delay difference between CK and DQS in Board Skew Parameters for LPDDR2/DDR2/DDR3 SDRAM section.
  • Revised content of Parameter Descriptions table in Board and Package Skews for LPDDR2/DDR3/DDR4 SDRAM for Arria 10 EMIF IP.
  • Revised content of Parameter Descriptions table in Board and Package Skews for QDR II, QDR II+, and QDR II+ Xtreme for Arria 10 EMIF IP.
  • Revised content of Parameter Descriptions table in Board and Package Skews for RLDRAM II and RLDRAM 3 for Arria 10 EMIF IP.
  • Revised content of Controller Settings table in Controller Settings for Arria 10 EMIF IP.
  • Added Diagnostics for Arria 10 EMIF IP.
December 2013 2013.12.16
  • Removed references to ALTMEMPHY.
  • Removed references to HardCopy.
  • Removed references to Stratix II devices.
  • Removed references to SOPC Builder.
  • Added Arria 10 information to Qsys Interface, Generated Files, Parameter Settings, Board Settings, and Controller Settings sections.
  • Added descriptions of several registered DIMM parameters to Memory Parameters for LPDDR2, DDR2, and DDR3 SDRAM table.
  • Added steps for compiling example project.
  • Added clock information to Adding Pins and DQ Group Assignments.
  • Updated Intersymbol Interference for UniPHY IP to Intersymbol Interference Channel Signal Integrity for UniPHY IP.
  • Added Intersymbol Interference Channel Signal Integrity for Arria 10 EMIF IP.
November 2012 6.0
  • Added RLDRAM 3 information.
  • Added LPDDR2 information.
  • Changed chapter number from 8 to 9.
June 2012 5.0
  • Added number of sharing interfaces parameters to Clock Parameters table.
  • Added DQ/DQS Package Deskew and Address/Command Package Deskew descriptions to Board Skew Parameters table.

  • Added equations for multiple boards to several parameter descriptions in Board Skew Parameters table.

  • Added Feedback icon.
November 2011 4.0
  • Updated Installation and Licensing section.
  • Combined Qsys and SOPC Builder Interfaces sections.
  • Combined parameter settings for DDR, DDR2, DDR3 SDRAM, QDRII SRAM, and RLDRAM II for both ALTMEMPHY and UniPHY IP.

  • Added parameter usage details to Parameterizing Memory Controllers with UniPHY IP section.

  • Moved Functional Description section for DDR, DDR2, DDR3 SDRAM, QDRII SRAM, and RLDRAM II to volume 3 of the External Memory Interface Handbook.

June 2011 3.0
  • Removed references to High-Performance Controller.
  • Updated High-Performance Controller II information.
  • Removed HardCopy III, HardCopy IV E, HardCopy IV GX, Stratix III, and Stratix IV support.

  • Updated Generated Files lists.
  • Added Qsys and SOPC Builder Interfaces section.
December 2010 2.1
  • Updated Design Flows and Generated Files information.

  • Updated Parameterizing Memory Controllers with UniPHY IP chapter

July 2010 2.0
  • Added information for new GUI parameters: Controller latency, Enable reduced bank tracking for area optimization, and Number of banks to track.

  • Removed information about IP Advisor. This feature is removed from the DDR/DDR2 SDRAM IP support for version 10.0.

February 2010 1.3 Corrected typos.
February 2010 1.2
  • Full support for Stratix IV devices.
  • Added timing diagrams for initialization and calibration stages for HPC.
November 2009 1.1 Minor corrections.
November 2009 1.0 Initial release.

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