External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

5.3.3. RLDRAM II Termination Schemes

The following table lists the recommended termination schemes for major CIO RLDRAM II memory interface signals. These signals include data (DQ), data mask (DM), clocks (CK, CK#, DK, DK#, QK, and QK#), address, bank address, and command (WE#, REF#, and CS#).
Table 44.  RLDRAM II Termination Recommendations for Arria II GZ, Arria V, Stratix III, Stratix IV, and Stratix V Devices 

Signal Type

HSTL 15/18 Standard  (1)  (2)  (3)  (4)

Memory End Termination

DK/DK# Clocks

Class I R50 NO CAL

100 -ohmDifferential

QK/QK# Clocks

Class I P50 CAL

ZQ50

Data (Write)

Class I R50 CAL

ODT

Data (Read)

Class I P50 CAL

ZQ50

Data Mask

Class I R50 CAL

ODT

CK/CK# Clocks

Class I R50 NO CAL

×1 = 100-ohm Differential  (9)

×2 = 200-ohm Differential  (10)

Address/Bank Address  (5)  (6)

Class I Max Current

50 -ohmParallel to VTT

Command (WE#, REF#)  (5)  (6)

Class I Max Current

50 -ohmParallel to VTT

Command (CS#)  (5)  (6)  (7)

Class I Max Current

50 -ohmParallel to VTT

or Pull-up to VDD

QVLD  (8)

Class I P50 CAL

ZQ50

Notes to Table:

  1. R is effective series output impedance.
  2. P is effective parallel input impedance.
  3. CAL is OCT with calibration.
  4. NO CAL is OCT without calibration.
  5. For width expansion configuration, the address and control signals are routed to 2 devices. Recommended termination is 50 -ohm parallel to VTT at the trace split of a balanced T or Y routing topology. Use a clamshell placement of the two RLDRAM II components to achieve minimal stub delays and optimum signal integrity. Clamshell placement is when two devices overlay each other by being placed on opposite sides of the PCB.
  6. The UniPHY default IP setting for this output is Max Current. A Class I 50 -ohm output with calibration output is typically optimal in single load topologies.
  7. Intel recommends that you use a 50 -ohmparallel termination to VTT if your design meets the power sequencing requirements of the RLDRAM II component. Refer to the RLDRAM II data sheet for further information.
  8. QVLD is not used in the RLDRAM II Controller with UniPHY implementations.
  9. ×1 is a single-device load.
  10. ×2 is a double-device load. An alternative option is to use a 100 -ohm differential termination at the trace split.
Note: Intel recommends that you simulate your specific design for your system to ensure good signal integrity.

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