External Memory Interface Handbook Volume 2: Design Guidelines

Download
ID 683385
Date 5/08/2017
Public
Document Table of Contents

1.1.19.3. Maximum Number of DDR3 SDRAM Interfaces Supported per FPGA

The following table lists the maximum number of ×8 DDR3 SDRAM components that can be fitted in the smallest and biggest devices and pin packages assuming the device is blank.

Each interface of size n, where n is a multiple of 8, consists of:

  • n DQ pins (including ECC)
  • n/8 DM pins
  • n/8 DQS, DQSn pin pairs
  • 17 address pins
  • 7 command pins (CAS#, RAS#, WE#, CKE, ODT, reset, and CS#)
  • 1 CK, CK# pin pair
Table 7.  Maximum Number of DDR3 SDRAM Interfaces Supported per FPGA

Device

Device Type

Package Pin Count

Maximum Number of Interfaces

Arria II GX

EP2AGX190

EP2AGX260

1,152

  • Four ×8 interfaces or one ×72 interface on each side
  • No DQ pins on left side

EP2AGX45

EP2AGX65

358

  • One ×16 interface on both top and bottom sides
  • On right side, one ×8 interface
  • No DQ pins on left side

Arria II GZ

EP2AGZ300

EP2AGZ350

EP2AGZ225

1,517

Four ×8 interfaces on each side

EP2AGZ300

EP2AGZ350

780

  • Three ×8 interfaces on both top and bottom sides
  • No DQ pins on left and right sides

Arria V

5AGXB1

5AGXB3

5AGXB5

5AGXB7

5AGTD3

5AGTD7

1,517

  • Two ×72 interfaces on both top and bottom sides
  • No DQ pins on left and right sides

5AGXA1

5AGXA3

672

  • One ×56 interface or two ×24 interfaces on top and bottom sides
  • One ×32 interface on the right side
  • No DQ pins on the left side

5AGXA5

5AGXA7

672

  • One ×56 interface or two ×24 interfaces on both top and bottom sides
  • No DQ pins on the left side

Arria V GZ

5AGZE5

5AGZE7

1,517

  • Two ×72 interfaces on both top and bottom sides
  • No DQ pins on left and right sides

5AGZE1

5AGZE3

780

  • On top side, four ×8 interfaces or one x72 interface
  • On bottom side, four ×8 interfaces or one x72 interface
  • No DQ pins on left and right sides

Cyclone V

5CGTD9

5CEA9

5CGXC9

1,152

  • One ×72 interface or two ×32 interfaces on each of the top, bottom, and right sides
  • No DQ pins on the left side

5CEA7

5CGTD7

5CGXC7

484

  • One ×48 interface or two ×16 interfaces on both top and bottom sides
  • One x8 interface on the right side
  • No DQ pins on the left side

MAX 10 FPGA

10M50D672

10M40D672

762

One x32 interface on the right side

10M50D256

10M40D256

10M25D256

10M16D256

256

One x8 interface on the right side

Stratix III

EP3SL340

1,760

  • Two ×72 interfaces on both top and bottom sides
  • One ×72 interface on both right and left sides

EP3SE50

484

  • Two ×8 interfaces on both top and bottom sides
  • Three ×8 interfaces on both right and left sides

Stratix IV

EP4SGX290

EP4SGX360

EP4SGX530

1,932

  • One ×72 interface on each side

or

  • One ×72 interface on each side and 2 additional ×72 wraparound interfaces only if sharing DLL and PLL resources

EP4SE530

EP4SE820

1,760

EP4SGX70

EP4SGX110

EP4SGX180

EP4SGX230

780

  • Three ×8 interfaces or one ×64 interface on both top and bottom sides
  • On left side, one ×48 interface or two ×8 interfaces
  • No DQ pins on right side

Stratix V

5SGXA5

5SGXA7

1,932

  • Two ×72 interfaces (800 MHz) on both top and bottom sides
  • No DQ pins on left and right sides

5SGXA3

5SGXA4

780

  • On top side, two ×8 interfaces
  • On bottom side, four ×8 interfaces
  • No DQ pins on left and right sides

Did you find the information on this page useful?

Characters remaining:

Feedback Message