External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

8.1. Simulation Options

The following simulation options are available with the example testbench to improve simulation speed:
  • Full calibration—Calibrates the same way as in hardware, and includes all phase, delay sweeps, and centering on every data bit.
    Note: Arria 10 EMIF full calibration simulation will be available in a future release of the Quartus Prime software.
  • Quick calibration—Calibrates the read and write latency only, skipping per bit deskew. (Not available for Arria 10 EMIF IP.)
  • Skip calibration—Provides the fastest simulation. It loads the settings calculated from the memory configuration and enters user mode.

By default, the UniPHY IP generates abstract PHY, which uses skip calibration regardless of the simulation options that you chose in the parameter editor.

Note: For proper simulation of DQS Tracking, you must enable either full calibration or quick calibration.

The following table lists typical simulation times implemented using UniPHY IP. The simulation times in the table are estimates based on average run times of a few example designs. The simulation times for your design may vary depending on the memory interface specifications, simulator, or the system you are using.

Table 493.  Typical Simulation Times Using UniPHY IP

Calibration Mode/Run Time (1)

Estimated Simulation Time

Small Interface (×8 Single Rank)

Large Interface (×72 Quad Rank)

Full

  • Full calibration
  • Includes all phase/delay sweeps and centering

10 minutes

~ 1 day

Quick

  • Scaled down calibration
  • Calibrate one pin

3 minutes

4 hours

Skip

  • Skip all calibration, jump to user mode
  • Preload calculated settings

3 minutes

20 minutes

Note to Table:

  1. Uses one loop of driver test. One loop of driver is approximately 600 read or write requests, with burst length up to 64.
  2. Simulation times shown in this table are approximate measurements made using Synopsys VCS. Simulation times can vary considerably, depending on the IP configuration, the simulator used, and the computer or server used.
Table 494.  Typical Simulation Times Using Arria 10 EMIF IP

Calibration Mode/Run Time (1)

Estimated Simulation Time

Small Interface (×8 Single Rank)

Large Interface (×72 Quad Rank)

Full

  • Full calibration
  • Includes all phase/delay sweeps and centering

20 minutes

~ 1 day

Skip

  • Skip all calibration, jump to user mode
  • Preload calculated settings

10 minutes

25 minutes

Abstract PHY

  • Replace PHY and external memory model with a single abstract PHY model.
  • IMPORTANT: External memory model is NOT used in this mode. No I/O switching occurs to the external memory model.

1 minute

5 minutes

Note to Table:

  1. Uses one loop of driver test. One loop of driver is approximately 600 read or write requests, with burst length up to 64.
  2. Simulation times shown in this table are approximate measurements made using Synopsys VCS. Simulation times can vary considerably, depending on the IP configuration, the simulator used, and the computer or server used.

For more information about steps to follow before simulating, modifying the vendor memory model, and simulation flow for UniPHY IPs, refer to the “Simulation Walkthrough with UniPHY IP”.

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