External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents
Give Feedback Compiling the Design

After constraining your design, compile your design in the Quartus Prime software to generate timing reports to verify whether timing has been met.

To compile the design, on the Processing menu, click Start Compilation.

After you have compiled the top-level file, you can perform RTL simulation or program your targeted Intel® device to verify the top-level file in hardware.

Note: In UniPHY-based memory controllers, the derive_pll_clocks command can affect timing closure if it is called before the memory controller files are loaded. Ensure that the Quartus Prime IP File (.qip) appears in the file list before any Synopsys Design Constraint Files (.sdc) files that contain derive_pll_clocks.

For more information about simulating the memory IP, refer to Simulating Memory IP.