External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

1.4.6.6. PLL Usage for DDR, DDR2, and DDR3 SDRAM Without Leveling Interfaces

The following table lists PLL usage for DDR, DDR2, and DDR3 protocols without leveling interfaces.
Table 23.  PLL Usage for DDR, DDR2, and DDR3 SDRAM Without Leveling Interfaces 

Clock

Arria II GX Devices

Stratix III and Stratix IV Devices

C0

  • phy_clk_1x in half-rate designs
  • aux_half_rate_clk
  • PLL scan_clk
  • phy_clk_1x in half-rate designs
  • aux_half_rate_clk
  • PLL scan_clk

C1

  • phy_clk_1x in full-rate designs
  • aux_full_rate_clk
  • mem_clk_2x to generate DQS and CK/CK# signals
  • ac_clk_2x
  • cs_n_clk_2x
  • mem_clk_2x

C2

  • Unused
  • phy_clk_1x in full-rate designs
  • aux_full_rate_clk

C3

  • write_clk_2x (for DQ)
  • ac_clk_2x
  • cs_n_clk_2x
  • write_clk_2x

C4

  • resync_clk_2x
  • resync_clk_2x

C5

  • measure_clk_2x
  • measure_clk_1x

C6

  • ac_clk_1x

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