External Memory Interface Handbook Volume 2: Design Guidelines

Download
ID 683385
Date 5/08/2017
Public
Document Table of Contents

3.3.2.3. Clock Group Signals

Like the control group signals, the clock signals in DDR3 SDRAM are only ever single rank loaded. A dual-rank capable DDR3 DIMM slot has two copies of the signal, and a dual-slot interface has four copies of the mem_clk and mem_clk_n signals.

For more information about a DDR3 two-DIMM system design, refer to Micron TN-41-08: DDR3 Design Guide for Two-DIMM Systems.

Did you find the information on this page useful?

Characters remaining:

Feedback Message