External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

1.4.5.4. LPDDR2 Pin Utilization for Arria V, Cyclone V, and MAX 10 FPGA Devices

The following table lists the FPGA pin utilization for LPDDR2 SDRAM.
Table 15.  LPDDR2 Pin Utilization for Arria V, Cyclone V, and MAX 10 FPGA Devices 

Interface Pin Description

Memory Device Pin Name

FPGA Pin Utilization

Memory Clock

CK, CKn

Differential clock inputs. All double data rate (DDR) inputs are sampled on both positive and negative edges of the CK signal. Single data rate (SDR) inputs are sampled at the positive clock edge. Place any unused DQ or DQS pins with DIFFOUT capability for the mem_clk[n:0] and mem_clk_n[n:0] signals (where n>=0). Do not place CK and CK# pins in the same group as any other DQ or DQS pins. If there are multiple CK and CK# pin pairs, place them on DIFFOUT in the same single DQ group of adequate width.

Address and Command

CA0-CA9

CSn

CKE

Unidirectional DDR command and address bus inputs. Chip Select: CSn is considered to be part of the command code.Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and therefore device input buffers and output drivers. Place address and command pins in any DDR-capable I/O pin. To minimize skew, Intel recommends using address and command pins in the same bank or side of the device as the CK/CK#, DQ. DQS, or DM pins..

Data

DQ0-DQ7 (×8)

DQ0-DQ15 (×16)

DQ0-DQ31 (×32)

Bidirectional data bus. Pins are used as data inputs and outputs. DQ in the pin table is marked as Q in the Pin Planner. Each DQ group has a common background color for all of the DQ and DM pins associated with DQS (and DQSn) pins. Place on DQ group pin marked Q in the Pin Planner.

Data Strobe

DQS, DQSn

Data Strobe. The data strobe is bidirectional (used for read and write data) and differential (DQS and DQSn). It is output with read data and input with write data. Place on DQS and DQSn (S and Sbar in the Pin Planner) for differential DQS signaling.

Data Mask

DM0 (×8)

DM0-DM1 (×16)

DM0-DM3 (×32)

Input Data Mask. DM is the input mask signal for write data. Input data is masked when DM is sampled HIGH coincident with that input data during a write access. DM is sampled on both edges of DQS. DQ in the pin table is marked as Q in the Pin Planner. Each DQ group has a common background color for all of the DQ and DM pins, associated with DQS (and DQSn) pins. Place on DQ group pin marked Q in the Pin Planner.

Clock Source

Dedicated PLL clock input pin with direct (not using a global clock net) connection to the PLL and optional DLL required by the interface.

Reset

Dedicated clock input pin to accommodate the high fan-out signal.

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