External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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Document Table of Contents

1.4.6.2. Number of Enhanced PLL Clock Outputs and Dedicated Clock Outputs Available in Intel® Device Families

The following table lists the number of enhanced PLL clock outputs and dedicated clock outputs available in Intel® device families.
Table 19.  Number of Enhanced PLL Clock Outputs and Dedicated Clock Outputs Available in Intel® Device Families (1)

Device Family

Number of Enhanced PLL Clock Outputs

Number Dedicated Clock Outputs

Arria II GX  (2)

7 clock outputs each

1 single-ended or 1 differential pair

3 single-ended or 3 differential pair total  (3)

Arria V

18 clock outputs each

4 single-ended or 2 single-ended and 1 differential pair

Stratix III

Left/right: 7 clock outputs

Top/bottom: 10 clock outputs

Left/right: 2 single-ended or 1 differential pair

Top/bottom: 6 single-ended or 4 single‑ended and 1 differential pair

Arria II GZ and Stratix IV

Left/right: 7 clock outputs

Top/bottom: 10 clock outputs

Left/right: 2 single-ended or 1 differential pair

Top/bottom: 6 single-ended or 4 single‑ended and 1 differential pair

Arria V GZ and Stratix V

18 clock outputs each

4 single-ended or 2 single-ended and 1 differential pair

Notes to Table:

  1. For more details, refer to the Clock Networks and PLL chapter of the respective device family handbook.
  2. PLL_5 and PLL_6 of Arria II GX devices do not have dedicated clock outputs.
  3. The same PLL clock outputs drives three single-ended or three differential I/O pairs, which are only supported in PLL_1 and PLL_3 of the EP2AGX95, EP2AGX125, EP2AGX190, and EP2AGX260 devices.

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