External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
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9.2. FPGA Timing Paths

The following topics describe the FPGA timing paths, the timing constraints examples, and the timing assumptions that the constraint scripts use.

In Arria II, Arria V, Arria V GZ, Cyclone V, Stratix III, Stratix IV, and Stratix V devices, the interface margin is reported based on a combination of the Timing Analyzer and further steps to account for calibration that occurs at runtime. First the timing analyzer returns the base setup and hold slacks, and then further processing adjusts the slacks to account for effects which cannot be modeled in the timing analyzer.