External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents
Give Feedback

9.9.5. Address and Command Timing

You can optimize the timing margins on the address and command timing path by changing the PLL phase shift used to generate these signals. In the DDR2 or DDR3 SDRAM Controllers with UniPHY IP cores, modify the Additional CK/CK# phase and Additional Address and Command clock phase parameters.

The DDR2 and DDR3 SDRAM memory controllers use 1T memory timing even in half-rate mode, which may affect the address command margins for DDR2 or DDR3 SDRAM designs that use memory DIMMs. DDR2 SDRAM designs have a greater impact because the address command bus fans out to all the memory devices on a DIMM increasing the loading effect on the bus. Make sure your board designs are robust enough to have the memory clock rising edge within the 1T address command window. You can also use the Additional Address and Command clock phase parameter to adjust the phase of the address and command if needed.

The far‑end load value and board trace delay differences between address and command and memory clock pins can result in timing failures if they are not accounted for during timing analysis.

The Quartus Prime Fitter may not optimally set output delay chains on the address and command pins. To ensure that any PLL phase‑shift adjustments are not negated by delay chain adjustments, create logic assignments using the Assignment Editor to set all address and command output pin D5 delay chains to 0.

For Stratix III and Stratix IV devices, some corner cases of device family and memory frequency may require an increase to the address and command clock phase to meet core timing. You can identify this situation, if the DDR timing report shows a PHY setup violation with the phy_clk launch clock, and the address and command latch clock—clock 0 (half-rate phy_clk) or 2 (full-rate phy_clk), and 6, respectively.

If you see this timing violation, you may fix it by advancing the address and command clock phase as required. For example, a 200-ps violation for a 400-MHz interface represents 8% of the clock period, or 28.8. Therefore, advance the address and command phase from 270 to 300. However, this action reduces the setup and hold margin at the DDR device.