External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

9.1.2. Calibrated Paths

Calibrated timing paths are those where the clock used to capture data is dynamically positioned within the data valid window (DVW) to maximize timing margin.

For UniPHY-based controllers and Arria 10 EMIF controllers, the sequencer block analyzes all path delays between the read capture registers and the read FIFO buffer to set up the FIFO write clock phase for optimal timing margin. The read postamble calibration process is implemented in a similar manner to the read resynchonization calibration. In addition, the sequencer block calibrates a read data valid signal to the delay between a controller issuing a read command and read data returning to controller.

In DDR2, DDR3, and RLDRAM II with UniPHY, and in Arria 10 EMIF, the IP calibrates the write-leveling chains and programmable output delay chain to align the DQS edge with the CK edge at memory to meet the tDQSS, tDSS, and tDSH specifications.

Both UniPHY IP and Arria 10 EMIF IP enable the dynamic deskew calibration with the Nios II sequencer for read and write paths. Dynamic deskew process uses the programmable delay chains that exist within the read and write data paths to adjust the delay of each DQ and DQS pin to remove the skew between different DQ signals and to centre-align the DQS strobe in the DVW of the DQ signals. This process occurs at power up for the read and the write paths.

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