External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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Document Table of Contents

6.5. QDR II SRAM Layout Approach

Using the layout guidelines in the above table, Intel recommends the following layout approach:
  1. Route the K/K# clocks and set the clocks as the target trace propagation delays for the output signal group.
  2. Route the write data output signal group (write data, byte write select), ideally on the same layer as the K/K# clocks, to within ±10 ps skew of the K/K# traces.
  3. Route the address/control output signal group (address, RPS, WPS), ideally on the same layer as the K/K# clocks, to within ±20 ps skew of the K/K# traces.
  4. Route the CQ/CQ# clocks and set the clocks as the target trace propagation delays for the input signal group.
  5. Route the read data output signal group (read data), ideally on the same layer as the CQ/CQ# clocks, to within ±10 ps skew of the CQ/CQ# traces.
  6. The output and input groups do not need to have the same propagation delays, but they must have all the signals matched closely within the respective groups.

The following tables list the typical margins for QDR II and QDR II+ SRAM interfaces, with the assumption that there is zero skew between the signal groups.

Table 53.  Typical Worst Case Margins for QDR II SRAM Interfaces of Burst Length 2

Device

Speed Grade

Frequency (MHz)

Typical Margin Address/Command (ps)

Typical Margin Write Data (ps)

Typical Margin Read Data (ps)

Arria II GX

I5

250

± 240

± 80

± 170

Arria II GX

×36 emulated

I5

200

± 480

± 340

± 460

Stratix IV

350

Stratix IV

×36 emulated

C2

300

± 320

± 170

± 340

Table 54.  Typical Worst Case Margins for QDR II+ SRAM Interfaces of Burst Length 4

Device

Speed Grade

Frequency (MHz)

Typical Margin Address/Command (ps)  (1)

Typical Margin Write Data (ps)

Typical Margin Read Data (ps)

Arria II GX

I5

250

± 810

± 150

± 130

Arria II GX

×36 emulated

I5

200

± 1260

± 410

± 420

Stratix IV

C2

400

± 550

± 10

± 80

Stratix IV

×36 emulated

C2

300

± 860

± 180

± 300

Note to Table:

  1. The QDR II+ SRAM burst length of 4 designs have greater margins on the address signals because they are single data rate.

Other devices and speed grades typically show higher margins than the ones in the above tables.

Note: Intel recommends that you create your project with a fully implemented QDR II or QDR II+ SRAM Controller with UniPHY interface, and observe the interface timing margins to determine the actual margins for your design.

Although the recommendations in this chapter are based on simulations, you can apply the same general principles when determining the best termination scheme, drive strength setting, and loading style to any board designs. Even armed with this knowledge, it is still critical that you perform simulations, either using IBIS or HSPICE models, to determine the quality of signal integrity on your designs.

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