9.11.6. PHY Reset Recovery and Removal
The UniPHY IP does not require any dedicated clock networks for reset signals. Only UniPHY PLL outputs require clock networks, and any other PHY signal using clock networks may result in timing violations.
You can correct such timing violations by:
- Setting the Global Signal logic assignment to Off for the problem path (using the Assignment Editor), or
- Adjusting the logic placement (using the Assignment Editor or Chip Planner)
Did you find the information on this page useful?