External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

9.11.6. PHY Reset Recovery and Removal

A common cause for reset timing violations in UniPHY designs is the selection of a global or regional clock network for a reset signal.

The UniPHY IP does not require any dedicated clock networks for reset signals. Only UniPHY PLL outputs require clock networks, and any other PHY signal using clock networks may result in timing violations.

You can correct such timing violations by:

  • Setting the Global Signal logic assignment to Off for the problem path (using the Assignment Editor), or
  • Adjusting the logic placement (using the Assignment Editor or Chip Planner)

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