External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
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9.11. Timing Deration Methodology for Multiple Chip Select DDR2 and DDR3 SDRAM Designs

In a multiple chip select system, each individual rank has its own chip select signal. Consequently, you must change the Total Memory chip selects, Number of chip select (for discrete components) or Number of chip select per slot (DIMMs) in the Preset Editor of the UniPHY-based parameter editors.

In the Preset Editor, you must leave the baseline non-derated tDS, tDH, tIS, tIH values, because the settings on the Board Settings page account for multiple chip select slew rate deration.

The following topics explain two timing deration methodologies for multiple chip-select DDR2 and DDR3 SDRAM designs:

  • Timing Deration using the Board Settings
  • Timing Deration Using the Excel-Based Calculator

For Arria II GX, Arria II GZ, Arria V GZ, Cyclone V, Stratix IV, and Stratix V devices, the UniPHY-based controller parameter editor has an option to select multiple chip-select deration.

Note: To perform multiple chip-select timing deration for other Intel devices (such as Stratix III devices), Intel provides an Excel-based

Timing deration in this section applies to either discrete components or DIMMs.

Note: You can derate DDR SDRAM multiple chip select designs by using the DDR2 SDRAM section of the Excel-based calculator, but Intel does not guarantee the results.

This section assumes you know how to obtain data on PCB simulations for timing deration from HyperLynx or any other PCB simulator.