External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

8.2.9. Simulation Issues

When you simulate an example design in ModelSim* , you might see the following warnings, which are expected and not harmful:
# ** Warning: (vsim-3015) 
D:/design_folder/iptest10/simulation/uniphy_s4/rtl/uniphy_s4_controller_phy.sv(402
): [PCDPC] - Port size (1 or 1) does not match connection size (7) for port
'local_size'.

#         Region: 
/uniphy_s4_example_top_tb/dut/mem_if/controller_phy_inst/alt_ddrx_controller_inst

# ** Warning: (vsim-3015) 
D:/design_folder/iptest10/simulation/uniphy_s4/rtl/uniphy_s4_controller_phy.sv(402
): [PCDPC] - Port size (9 or 9) does not match connection size (1) for port
'ctl_cal_byte_lane_sel_n'.

#         Region:
 /uniphy_s4_example_top_tb/dut/mem_if/controller_phy_inst/alt_ddrx_controller_inst

# ** Warning: (vsim-3015) 
D:/design_folder/iptest10/simulation/uniphy_s4/rtl/uniphy_s4_controller_phy.sv(402
): [PCDPC] - Port size (18 or 18) does not match connection size (1) for port
'afi_doing_read'.

#         Region:
 /uniphy_s4_example_top_tb/dut/mem_if/controller_phy_inst/alt_ddrx_controller_inst

# ** Warning: (vsim-3015)
D:/design_folder/iptest10/simulation/uniphy_s4/rtl/uniphy_s4_controller_phy.sv(402
): [PCDPC] - Port size (2 or 2) does not match connection size (1) for port
'afi_rdata_valid'.

#         Region: 
/uniphy_s4_example_top_tb/dut/mem_if/controller_phy_inst/alt_ddrx_controller_inst

# ** Warning: (vsim-3015)
 D:/design_folder/iptest10/simulation/uniphy_s4/rtl/uniphy_s4_controller_phy.sv(402
): [PCDPC] - Port size (112 or 112) does not match connection size (1) for port
'bank_information'.

#         Region: 
/uniphy_s4_example_top_tb/dut/mem_if/controller_phy_inst/alt_ddrx_controller_inst

# ** Warning: (vsim-3015) 
D:/design_folder/iptest10/simulation/uniphy_s4/rtl/uniphy_s4_controller_phy.sv(402
): [PCDPC] - Port size (8 or 8) does not match connection size (1) for port
'bank_open'.

#         Region:
/uniphy_s4_example_top_tb/dut/mem_if/controller_phy_inst/alt_ddrx_controller_inst

# ** Warning: (vsim-3017)
D:/design_folder/iptest10/simulation/uniphy_s4/rtl/uniphy_s4_alt_ddrx_bank_timer_
wrapper.v(1191): [TFMPC] - Too few port connections. Expected 127, found 126.

#         Region: 
/uniphy_s4_example_top_tb/dut/mem_if/controller_phy_inst/alt_ddrx_controller_inst
/bank_timer_wrapper_inst/bank_timer_inst

# ** Warning: (vsim-3722) 
D:/design_folder/iptest10/simulation/uniphy_s4/rtl/uniphy_s4_alt_ddrx_bank_timer_
wrapper.v(1191): [TFMPC] - Missing connection for port 'wr_to_rd_to_pch_all'.

# ** Warning: (vsim-3015) 
D:/design_folder/iptest10/simulation/uniphy_s4/rtl/uniphy_s4_alt_ddrx_bank_timer_
wrapper.v(1344): [PCDPC] - Port size (5 or 5) does not match connection size (1) 
for port 'wr_to_rd_to_pch_all'.

#         Region: 
/uniphy_s4_example_top_tb/dut/mem_if/controller_phy_inst/alt_ddrx_controller_
inst/bank_timer_wrapper_inst/rank_monitor_inst

# ** Warning: (vsim-8598) Non-positive replication multiplier inside concat. 
Replication will be ignored

Warning-[OSPA-N] Overriding same parameter again

/p/eda/acd/altera/quartusII/10.1/quartus/eda/sim_lib/synopsys/stratixv_atoms_
ncrypt.v, 8499

Warning-[ZONMCM] Zero or negative multiconcat multiplier
../quartus_stratix5/ddr3_ctlr_sim/ddr3_ctlr_sequencer.sv, 916

Zero or negative multiconcat multiplier is found in design. It will be 
replaced by 1'b0.

  Source info: {INIT_COUNT_WIDTH {1'b0}}

Warning-[PCWM-W] Port connection width mismatch 
../quartus_stratix5/ddr3_ctlr_sim/ddr3_ctlr_sequencer_cpu.v, 2830

"the_sequencer_cpu_nios2_oci_itrace"

The following 38-bit expression is connected to 16-bit port "jdo" of module
"ddr3_ctlr_sequencer_cpu_nios2_oci_itrace", instance   
"the_sequencer_cpu_nios2_oci_itrace".

Expression: jdo
use  +lint=PCWM for more details

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