External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

3.2.1. Overview of ODT Control

When there is only a single-DIMM on the board, the ODT control is relatively straightforward. During write to the memory, the ODT feature of the memory is turned on; during read from the memory, the ODT feature of the memory is turned off. However, when there are multiple DIMMs on the board, the ODT control becomes more complicated.

With a dual-DIMM interface on the system, the controller has different options for turning the memory ODT on or off during read or write. The following table lists the DDR2 SDRAM ODT control during write to the memory. These DDR2 SDRAM ODT controls are recommended by Samsung Electronics. The JEDEC DDR2 specification was updated to include optional support for RTT(nominal) = 50-ohm.

For more information about the DDR2 SDRAM ODT controls recommended by Samsung, refer to the Samsung DDR2 Application Note: ODT (On Die Termination) Control.

Table 36.   DDR2 SDRAM ODT Control—Writes  (1)

Slot 1 (2)

Slot 2 (2)

Write To

FPGA

Module in Slot 1

Module in Slot 2

Rank 1

Rank 2

Rank 3

Rank 4

DR

DR

Slot 1

Series 50-ohms

Infinite

Infinite

75 or 50-ohm

Infinite

Slot 2

Series 50-ohms

75 or 50-ohm

Infinite

Infinite

Infinite

SR

SR

Slot 1

Series 50-ohms

Infinite

Unpopulated

75 or 50-ohm

Unpopulated

Slot 2

Series 50-ohms

75 or 50-ohm

Unpopulated

Infinite

Unpopulated

DR

Empty

Slot 1

Series 50-ohms

150-ohm

Infinite

Unpopulated

Unpopulated

Empty

DR

Slot 2

Series 50-ohms

Unpopulated

Unpopulated

150-ohm

Infinite

SR

Empty

Slot 1

Series 50-ohms

150-ohm

Unpopulated

Unpopulated

Unpopulated

Empty

SR

Slot 2

Series 50-ohms

Unpopulated

Unpopulated

150-ohm

Unpopulated

Notes to Table:

  1. For DDR2 at 400 MHz and 533 Mbps = 75-ohm; for DDR2 at 667 MHz and 800 Mbps = 50-ohm.
  2. SR = single ranked; DR = dual ranked.
Table 37.   DDR2 SDRAM ODT Control—Reads  (1)

Slot 1 (2)

Slot 2 (2)

Read From

FPGA

Module in Slot 1

Module in Slot 2

Rank 1

Rank 2

Rank 3

Rank 4

DR

DR

Slot 1

Parallel 50-ohms

Infinite

Infinite

75 or 50-ohm

Infinite

Slot 2

Parallel 50-ohms

75 or 50-ohm

Infinite

Infinite

Infinite

SR

SR

Slot 1

Parallel 50-ohms

Infinite

Unpopulated

75 or 50-ohm

Unpopulated

Slot 2

Parallel 50-ohms

75 or 50-ohm

Unpopulated

Infinite

Unpopulated

DR

Empty

Slot 1

Parallel 50-ohms

Infinite

Infinite

Unpopulated

Unpopulated

Empty

DR

Slot 2

Parallel 50-ohms

Unpopulated

Unpopulated

Infinite

Infinite

SR

Empty

Slot 1

Parallel 50-ohms

Infinite

Unpopulated

Unpopulated

Unpopulated

Empty

SR

Slot 2

Parallel 50-ohms

Unpopulated

Unpopulated

Infinite

Unpopulated

Notes to Table:

  1. For DDR2 at 400 MHz and 533 Mbps = 75-ohm; for DDR2 at 667 MHz and 800 Mbps = 50-ohm.
  2. SR = single ranked; DR = dual ranked.

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