External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

7.3.3.2.2. Memory Initialization Options for DDR3

Memory Initialization Options—DDR3

Mirror Addressing: 1 per chip select

Specifies the mirror addressing for multiple rank DIMMs. Refer to memory vendor data sheet for more information. Enter ranks with mirrored addresses in this field. For example, for four chip selects, enter 1101 to mirror the address on chip select #3, #2, and #0.

Address and command parity

Enables address/command parity checking to detect errors in data transmission. This is required for registered DIMM (RDIMM).

Mode Register 0

Read burst type

Specifies accesses within a given burst in sequential or interleaved order.

Specify sequential ordering for use with the Intel memory controller. Specify interleaved ordering only for use with an interleaved-capable custom controller, when the Generate PHY only parameter is enabled on the PHY Settings tab.

DLL precharge power down

Specifies whether the DLL in the memory device is off or on during precharge power-down.

Memory CAS latency setting

The number of clock cycles between the read command and the availability of the first bit of output data at the memory device and also interface frequency. Refer to memory vendor data sheet speed bin table.

Set this parameter according to the target memory speed grade and memory clock frequency.

Mode Register 1

Output drive strength setting

The output driver impedance setting at the memory device.

To obtain the optimum signal integrity performance, select the optimum setting based on the board simulation results.

Memory additive CAS latency setting

The posted CAS additive latency of the memory device.

Enable this feature to improve command and bus efficiency, and increase system bandwidth. For more information, refer to the Optimizing the Controller chapter.

ODT Rtt nominal value

The on-die termination resistance at the memory device.

To obtain the optimum signal integrity performance, select the optimum setting based on the board simulation results.

Mode Register 2

Auto selfrefresh method

Disable or enable auto selfrefresh.

Selfrefresh temperature

Specifies the selfrefresh temperature as Normal or Extended.

Memory write CAS latency setting

The number of clock cycles from the releasing of the internal write to the latching of the first data in, at the memory device and also interface frequency. Refer to memory vendor data sheet speed bin table and set according to the target memory speed grade and memory clock frequency.

Dynamic ODT (Rtt_WR) value

The mode of the dynamic ODT feature of the memory device. This is used for multi-rank configurations. Refer to DDR2 and DDR3 SDRAM Board Layout Guidelines.

To obtain the optimum signal integrity performance, select the optimum setting based on the board simulation results.

DDR3 RDIMM/LRDIMM Control Words

The memory device features a set of control words of SSTE32882 registers. These 4-bit control words of serial presence-detect (SPD) information allow the controller to optimize device properties to match different DIMM net topologies.

You can obtain the control words from the memory manufacturer's data sheet. You enter each word in hexadecimal, starting with RC15 on the left and ending with RC0 on the right.

Note: This parameter is not available for MAX 10 devices.

LRDIMM Additional Control Words

The memory device features a set of control words of SSTE32882 registers. These 4-bit control words of serial presence-detect (SPD) information allow the controller to optimize device properties to match different DIMM net topologies.

You can obtain the control words from the memory manufacturer's data sheet. You enter each word in hexadecimal, starting with SPD (77-72) or SPD(83-78) on the left and ending with SPD(71-69) on the right.

Note: This parameter is not available for MAX 10 devices.

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