External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents
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4.1.1. LPDDR2 SDRAM Configurations

The LPDDR2 SDRAM Controller with UniPHY Intel FPGA IP supports interfaces for LPDDR2 SDRAM with a single device, and multiple devices up to a maximum width of 32 bits.

When using multiple devices, a balanced-T topology is recommended for the signal connected from single point to multiple point, to maintain equal flight time.

You should connect a 200 ohm differential termination resistor between CK/CK# in multiple device designs as shown in the second figure below, to maintain an effective resistance of 100 ohms.

You should also simulate your multiple device design to obtain the optimum drive strength settings and ensure correct operation.

The following figure shows the main signal connections between the FPGA and a single LPDDR2 SDRAM component.

Figure 41. Configuration with a Single LPDDR2 SDRAM Component

Note to Figure:

  1. Use external discrete termination, as shown for CKE, but you may require a pull-down resistor to GND. Refer to the LPDDR2 SDRAM device data sheet for more information about LPDDR2 SDRAM power-up sequencing.

The following figure shows the differential resistor placement for CK/CK# for multi-point designs.

Figure 42. CK Differential Resistor Placement for Multi Point Design

Note to Figure:

  1. Place 200-ohm differential resistors near the memory devices at the end of the last board trace segments.

The following figure shows the detailed balanced topology recommended for the address and command signals in the multi-point design.

Figure 43. Address Command Balanced-T Topology

Notes to Figure:

  1. Split the trace close to the memory devices to minimize signal reflections and impedence nonuniformity.
  2. Keep the TL2 traces as short as possible, so that the memory devices appear as a single load.