External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
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9.2.2. Stratix III and Stratix IV PHY Timing Paths

A close look at all the register transfers occurring in the Stratix III and Stratix IV input datapath reveals many source-synchronous and calibrated circuits.
Note: The information in the following figure and table is based on Stratix IV devices, but is also applicable to Stratix III devices.

The following figure shows a block diagram of this input path with some of these paths identified for Stratix IV devices. The output datapath contains a similar set of circuits.

Note: UniPHY IP interfaces bypass the alignment and synchronization registers.
Figure 69. Stratix IV Input Path Registers and Circuit Types in SDRAM Interface


The following table lists the timing paths applicable for an interface between Stratix IV devices and half-rate SDRAM components.

Note: The timing paths are also applicable to Stratix III devices, but Stratix III devices use only source-synchronous path for read and write data paths.
Table 496.  Stratix IV External Memory Interface Timing Paths   (Part 1 of 2)

Timing Path

Circuit Category

Source

Destination

Read Data  (1)

Source‑Synchronous and Calibrated

Memory DQ, DQS Pins

DQ Capture Registers in IOE

Write Data  (1)

Source‑Synchronous and Calibrated

FPGA DQ, DQS Pins

Memory DQ, DM, and DQS Pins

Address and command  (1)

Source‑Synchronous

FPGA CK/CK# and Addr/Cmd Pins

Memory Input Pins

Clock-to-Strobe  (1)

Source‑Synchronous

FPGA CK/CK# and DQS Output Pins

Memory Input Pins

Read Resynchronization  (1)

Calibrated

IOE Capture Registers

IOE Alignment and Resynchronization Registers

Read Resynchronization  (1)  (4)

Calibrated

IOE Capture Registers

Read FIFO in FPGA Core

PHY IOE-Core Paths  (1)

Source‑Synchronous

IOE Half Data Rate Registers and Half‑Rate Resynchronization Clock

FIFO in FPGA Core

PHY & Controller Internal Paths  (1)

Internal Clock fMAX

Core registers

Core registers

I/O Toggle Rate  (2)

I/O – Data sheet

FPGA Output Pin

Memory Input Pins

Output Clock Specifications (Jitter, DCD)  (3)

I/O – Data sheet

FPGA Output Pin

Memory Input Pins

Notes to Table:

  1. Timing margins for this path are reported by the TimeQuest Timing Analyzer Report DDR function.
  2. Intel recommends that you perform signal integrity simulations to verify I/O toggle rate.
  3. For output clock specifications, refer to theDC and Switching Characteristics chapter of the Stratix IV Device Handbook.
  4. Only for UniPHY IP.

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