External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

5. RLDRAM II and RLDRAM 3 Board Design Guidelines

The following topics provide layout guidelines for you to improve your system's signal integrity and to successfully implement an RLDRAM II or RLDRAM 3 interface.

The RLDRAM II Controller with UniPHY intellectual property (IP) enables you to implement common I/O (CIO) RLDRAM II interfaces with Arria® V, Stratix® III, Stratix IV, and Stratix V devices. The RLDRAM 3 UniPHY IP enables you to implement CIO RLDRAM 3 interfaces with Stratix V and Arria V GZ devices. You can implement separate I/O (SIO) RLDRAM II or RLDRAM 3 interfaces with the ALTDQ_DQS or ALTDQ_DQS2 IP cores.

The following topics focus on the following key factors that affect signal integrity:

  • I/O standards
  • RLDRAM II and RLDRAM 3 configurations
  • Signal terminations
  • Printed circuit board (PCB) layout guidelines

I/O Standards

RLDRAM II interface signals use one of the following JEDEC I/O signalling standards:

  • HSTL-15—provides the advantages of lower power and lower emissions.
  • HSTL-18—provides increased noise immunity with slightly greater output voltage swings.

RLDRAM 3 interface signals use the following JEDEC I/O signalling standards: HSTL 1.2 V and SSTL-12.

To select the most appropriate standard for your interface, refer to the following:

  • Device Data Sheet for Arria II Devices chapter in the Arria II Device Handbook
  • Device Data Sheet for Arria V Devices chapter in the Arria V Device Handbook
  • Stratix III Device Data Sheet: DC and Switching Characteristics chapter in the Stratix III Device Handbook
  • DC and Switching Characteristics for Stratix IV Devices chapter in the Stratix IV Device Handbook
  • DC and Switching Characteristics for Stratix V Devices chapter in the Stratix V Device Handbook

The RLDRAM II Controller with UniPHY IP defaults to HSTL 1.8 V Class I outputs and HSTL 1.8 V inputs. The RLDRAM 3 UniPHY IP defaults to HSTL 1.2 V Class I outputs and HSTL 1.2 V inputs.

Note: The default for RLDRAM 3 changes from Class I to Class II, supporting up to 933 MHz, with the release of the Quartus II software version 12.1 SP1.

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