1.1.19. Maximum Number of Interfaces
Unless otherwise noted, the calculation for the maximum number of interfaces is based on independent interfaces where the address or command pins are not shared. The maximum number of independent interfaces is limited to the number of PLLs each FPGA device has.
For interface information for Arria 10 and Stratix 10 devices, you can consult the EMIF Device Selector on www.altera.com.
Timing closure depends on device resource and routing utilization. For more information about timing closure, refer to the Area and Timing Optimization Techniques chapter in the Quartus Prime Handbook.
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