External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

8.2.8. Post-fit Functional Simulation

The post-fit functional simulation does not work for the UniPHY IP core because of the following inherent problems:
  • The UniPHY sample 'X's during calibration, in which causes an issue during timing simulation
  • Some internal transfers that are 0-cycle require delays to properly function in a post-fit netlist

To enable functional simulation for a design that uses UniPHY IP core, a quasi-post-fit scheme is implemented. This scheme allows gate-level simulation of the full design (excluding the UniPHY IP), while you use RTL simulation for the UniPHY IP. The quasi‑post-fit scheme involves partitioning blocks in the EMIF and swaping them with simulation RTL. With this workaround the memory interface is partially post-fit RTL and partially premap RTL, therefore the simulation flow is not impeded.

Gate simulation for the hard memory controller is not supported.

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