External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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Document Table of Contents

7.3.4.2. Intersymbol Interference Channel Signal Integrity for UniPHY IP

Channel signal integrity is a measure of the distortion of the eye due to intersymbol interference or crosstalk or other effects.

Typically, when going from a single-rank configuration to a multi-rank configuration there is an increase in the channel loss, because there are multiple stubs causing reflections. Although the Quartus Prime timing models include some channel uncertainty, you must perform your own channel signal integrity simulations and enter the additional channel uncertainty, relative to the reference eye, into the parameter editor GUI.

For details about measuring channel loss parameters and entering channel signal integrity information into the parameter editor GUI, refer to the Wiki: http://www.alterawiki.com/wiki/Measuring_Channel_Signal_Integrity.

The following table lists intersymbol interference parameters.

Table 78.  ISI Parameters 

Parameter

Description

Derating method

Choose between default Intel settings (with specific Intel boards) or manually enter board simulation numbers obtained for your specific board.

This option is supported in LPDDR2/DDR2/DDR3 SDRAM only.

Address and command eye reduction (setup)

The reduction in the eye diagram on the setup side (or left side of the eye) due to ISI on the address and command signals compared to a case when there is no ISI. (For single rank designs, ISI can be zero; in multirank designs, ISI is necessary for accurate timing analysis.)

For more information about how to measure the ISI value for the address and command signals, refer to the “Measuring Eye Reduction for Address/Command, DQ, and DQS Setup and Hold Time” section in Analyzing Timing of Memory IP .

Address and command eye reduction (hold)

The reduction in the eye diagram on the hold side (or right side of the eye) due to ISI on the address and command signals compared to a case when there is no ISI.

For more information about how to measure the ISI value for the address and command signals, refer to “Measuring Eye Reduction for Address/Command, DQ, and DQS Setup and Hold Time” section in Analyzing Timing of Memory IP.

DQ/ D eye reduction

The total reduction in the eye diagram due to ISI on DQ signals compared to a case when there is no ISI. Intel assumes that the ISI reduces the eye width symmetrically on the left and right side of the eye.

For more information about how to measure the ISI value for the address and command signals, refer to “Measuring Eye Reduction for Address/Command, DQ, and DQS Setup and Hold Time” section in Analyzing Timing of Memory IP .

Delta DQS/Delta K/ Delta DK arrival time

The increase in variation on the range of arrival times of DQS compared to a case when there is no ISI. Intel assumes that the ISI causes DQS to further vary symmetrically to the left and to the right.

For more information about how to measure the ISI value for the address and command signals, refer to “Measuring Eye Reduction for Address/Command, DQ, and DQS Setup and Hold Time” section in Analyzing Timing of Memory IP .

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