External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

7.3.2. Generated Files for Memory Controllers with the UniPHY IP

When you complete the IP generation flow, there are generated files created in your project directory. The directory structure created varies somewhat, depending on the tool used to parameterize and generate the IP.
Note: The PLL parameters are statically defined in the <variation_name>_parameters.tcl at generation time. To ensure timing constraints and timing reports are correct, when you edit the PLL parameters, apply those changes to the PLL parameters in this file.

The following table lists the generated directory structure and key files created with the IP Catalog and Qsys.

Table 62.  Generated Directory Structure and Key Files for the IP Catalog Synthesis Files

Directory

File Name

Description

<working_dir>/

<variation_name>.qip

Quartus Prime IP file which refers to all generated files in the synthesis fileset. Include this file in your Quartus Prime project.

<working_dir>/

<variation_name>.v or <variation_name>.vhd

Top-level wrapper synthesis files.

.v is IEEE Encrypted Verilog.

.vhd is generated VHDL.

<working_dir>/<variation_name>/

<variation_name>_0002.v

UniPHY top-level wrapper.

<working_dir>/<variation_name>/

*.v, *.sv, *.tcl, *.sdc, *.ppf

RTL and constraints files for synthesis.

<working_dir>/<variation_name>/

<variation_name>_p0_pin_assignments.tcl

Pin constraints script to be run after synthesis.

Table 63.  Generated Directory Structure and Key Files for the IP Catalog Simulation Files

Directory

File Name

Description

<working_dir>/<variation_name>_sim/

<variation_name>.v

Top-level wrapper simulation files for both Verilog and VHDL.

<working_dir>/<variation_name>_sim/<subcomponent_module>/

*.v, *.sv, *.vhd, *.vho,*hex, *.mif

RTL and constraints files for simulation.

.v and .sv files are IEEE Encrypted Verilog.

.vhd and .vho are generated VHDL.

Table 64.  Generated Directory Structure and Key Files for the IP Catalog—Example Design Fileset Synthesis Files

Directory

File Name

Description

<variation_name>_example_design/example_project/

<variation_name>_example.qip

Quartus Prime IP file that refers to all generated files in the synthesizable project.

<variation_name>_example_design/example_project/

<variation_name>_example.qpf

Quartus Prime project for synthesis flow.

<variation_name>_example_design/example_project/

<variation_name>_example.qsf

Quartus Prime project for synthesis flow.

<variation_name>_example_design/example_project/ <variation_name>_example/

<variation_name>_example.v

Top-level wrapper.

<variation_name>_example_design/example_project/ <variation_name>_example/ submodules/

*.v, *.sv, *.tcl, *.sdc, *.ppf

RTL and constraints files.

<variation_name>_example_design/example_project/ <variation_name>_example/ submodules/

<variation_name>_example_if0_p0_pin_assignments.tcl

Pin constraints script to be run after synthesis.

_if0 and _p0 are instance names.

Table 65.  Generated Directory Structure and Key Files for the IP Catalog—Example Design Fileset Simulation Files

Directory

File Name

Description

<variation_name>_example_design/simulation/

generate_sim_verilog_example_design.tcl

Run this file to generate the Verilog simulation example design.

<variation_name>_example_design/simulation/

generate_sim_vhdl_example_design.tcl

Run this file to generate the VHDL simulation example design.

<variation_name>_example_design/simulation/

README.txt

A text file with instructions about how to generate and run the simulation example design.

<variation_name>_example_design/simulation/verilog/mentor

run.do

ModelSim* script to simulate the generated Verilog example design.

<variation_name>_example_design/simulation/vhdl/mentor

run.do

ModelSim* script to simulate the generated VHDL example design.

<variation_name>_example_design/simulation/verilog/ <variation_name>_sim/

<variation_name>_example_ sim.v

Top-level wrapper (Testbench) for Verilog.

<variation_name>_example_design/simulation/vhdl/ <variation_name>_sim/

<variation_name>_example_ sim.vhd

Top-level wrapper (Testbench) for VHDL.

<variation_name>_example_design/simulation/ <variation_name>_sim/verilog/ submodules/

*.v, *.sv, *.hex, *.mif

RTL and ROM data for Verilog.

<variation_name>_example_design/simulation/ <variation_name>_sim/vhdl/ submodules/

*.vhd, *.vho, *.hex, *.mif

RTL and ROM data for VHDL.

Table 66.  Generated Directory Structure and Key Files for Qsys

Directory

File Name

Description

<working_dir>/<system_name>/synthesis/

<system_name>.qip

Quartus Prime IP file that refers to all the generated files in the synthesis fileset.

<working_dir>/<system_name>/synthesis/

<system_name>.v

System top-level RTL for synthesis.

<working_dir>/<system_name>/simulation/

<system_name>.v or <variation_name>.vhd

System top-level RTL for simulation.

.v file is IEEE Encrypted Verilog.

.vhd file is generated VHDL.

<working_dir>/<system_name>/synthesis/ submodules/

*.v, *.sv, *.tcl, *.sdc, *.ppf

RTL and constraints files for synthesis.

<working_dir>/<system_name>/simulation/ submodules/

*.v, *.sv, *.hex, *.mif

RTL and ROM data for simulation.

The following table lists the prefixes or instance names of submodule files within the memory interface IP. These instances are concatenated to form unique synthesis and simulation filenames.

Table 67.  Prefixes of Submodule Files 

Prefixes

Description

_c0

Specifies the controller.

_d0

Specifies the driver or traffic generator.

_dll0

Specifies the DLL.

_e0

Specifies the example design.

_if0

Specifies the memory Interface.

_m0

Specifies the AFI mux.

_oct0

Specifies the OCT.

_p0

Specifies the PHY.

_pll0

Specifies the PLL.

_s0

Specifies the sequencer.

_t0

Specifies the traffic generator status checker.

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