External Memory Interface Handbook Volume 2: Design Guidelines

Download
ID 683385
Date 5/08/2017
Public
Document Table of Contents

7.3.3.7. Memory Timing Parameters for RLDRAM II for UniPHY IP

The following table lists the memory timing parameters for RLDRAM II.

Use the Memory Timing tab to apply the memory timings from your memory manufacturer’s data sheet.

Table 74.  Memory Timing Parameters

Parameter

Description

RLDRAM II

Maximum memory clock frequency

The maximum frequency at which the memory device can run. Set according to memory speed grade. Refer to memory data sheet.

Refresh interval

The refresh interval. Set according to memory speed grade. Refer to memory data sheet.

tCKH (%)

The input clock (CK/CK#) high expressed as a percentage of the full clock period. Set according to memory speed grade. Refer to memory data sheet.

tQKH (%)

The read clock (QK/QK#) high expressed as a percentage of tCKH. Set according to memory speed grade. Refer to memory data sheet.

tAS

Address and control setup to CK clock rise. Set according to memory speed grade. Refer to memory data sheet.

tAH

Address and control hold after CK clock rise. Set according to memory speed grade. Refer to memory data sheet.

tDS

Data setup to clock (CK/CK#) rise. Set according to memory speed grade. Refer to memory data sheet.

tDH

Data hold after clock (CK/CK#) rise. Set according to memory speed grade. Refer to memory data sheet.

tQKQ_max

QK clock edge to DQ data edge (in same group). Set according to memory speed grade. Refer to memory data sheet.

tQKQ_min

QK clock edge to DQ data edge (in same group). Set according to memory speed grade. Refer to memory data sheet.

tCKDK_max

Clock to input data clock (max). Set according to memory speed grade. Refer to memory data sheet.

tCKDK_min

Clock to input data clock (min). Set according to memory speed grade. Refer to memory data sheet.

Did you find the information on this page useful?

Characters remaining:

Feedback Message