External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
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1.2.6.5. Clock Network Usage in UniPHY-based Memory Interfaces—RLDRAM II, and QDR II and QDR II+ SRAM

The following table lists clock network usage in UniPHY-based memory interfaces for RLDRAM II, QDR II, and QDR II+ protocols.
Table 21.  Clock Network Usage in UniPHY-based Memory Interfaces—RLDRAM II, and QDR II and QDR II+ SRAM

Device

RLDRAM II

QDR II/QDR II+ SRAM

Half-Rate

Full-Rate

Half-Rate

Full-Rate

Number of full-rate clock

Number of half-rate clock

Number of full-rate clock

Number of full-rate clock

Number of half-rate clock

Number of full-rate clock

Arria II GX

2 global

2 global

4 global

Stratix III

2 regional

1 global

1 regional

1 global

2 regional

1 global

1 regional

2 regional

1 global

2 regional

Arria II GZ and Stratix IV

2 regional

1 global

1 regional

1 global

2 regional

1 global

1 regional

2 regional

1 global

2 regional

Note: For more information about the clocks used in UniPHY-based memory standards, refer to the Functional Description—UniPHY chapter in volume 3 of the External Memory Interface Handbook.