External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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Document Table of Contents

11.2.15. Efficiency Monitor

The Efficiency Monitor and Protocol Checker measures traffic efficiency on the Avalon interface between the traffic generator and the controller, and checks that the Avalon protocol is not violated.

The Protocol Checker monitors the controller’s Avalon slave interface for any illegal commands presented to it by any master; it does not monitor the legality of the controller’s Avalon outputs.

Figure 114. Efficiency Monitor and Protocol Checker Statistics


Note: To enable efficiency measurements to be performed on the controller Avalon interface through UniPHY External Memory Interface Toolkit, turn on Enable the Efficiency Monitor and Protocol Checker on the Controller Avalon Interface.
Note: For UniPHY-based designs, the efficiency monitor is not available for QDR II and QDR II+ SRAM interfaces, or for the MAX 10 device family, or for Arria V or Cyclone V designs using the Hard Memory Controller.
Note: The efficiency monitor does not take refreshes into account.

The Efficiency Monitor counts the number of cycles of command transfers and wait times for the controller interface and provides an Avalon slave port to allow access to this data. The efficiency monitor has an internal 32-bit counter for accessing transactions; its status can be any of the following:

  • Not Running
  • Not Running: Waiting for pattern start
  • Running
  • Not Running: Counter Saturation

For example, once the counter saturates the efficiency monitor stops because it can no longer track transactions. In the summary panel, this appears as Not Running: Counter Saturation.

The debug toolkit summarizes efficiency monitor statistics as follows:

  • Efficiency Monitor Cycle Count – counts cycles from first command/start until 232 or a stop request
  • Transfer Count – counts any data transfer cycle, read or write
  • Write Count – counts how many writes requested, including those during a burst
  • Read Count – counts how many reads requested (just commands)
  • Read Burst counter – counts how many reads requested (total burst requests)
  • Non-Transfer Cycle Waitrequest Count counts Non Transfer Cycles due to slave wait request high. A Non-Transfer Cycle is a cycle during which no read data is received and no write data is accepted on the Avalon interface.
  • Non-Transfer Cycle No readdatavalid Count counts Non Transfer Cycles due to slave not having read data
  • Non-Transfer Cycle Master Write Idle Count – counts Non Transfer Cycles due master not issuing command or pause in write burst
  • Non-Transfer Cycle Master Idle Count – counts Non Transfer Cycles due master not issuing command anytime
  • System Efficiency – The percentage of all Avalon-MM cycles where the interface is transferring data. Refreshes and idle time are not taken into consideration when calculating efficiency.
  • System Efficiency (During user access) Tracks the efficiency when transactions are occurring, which is a reflection on waitrequest. It is defined as: Transfer Count/(Efficiency Monitor Cycle Count - Non-Transfer Cycle Master Idle Count)
  • Minimum Read Latency The lowest of all read latencies, which is measured by time between a read command is being accepted by the Controller till the first beat of read data is presented to the driver.
  • Maximum Read Latency The highest of all read latencies, which is measured by time between a read command is being accepted by the Controller till the first beat of read data is presented to the driver.
  • Average Read Latency The average of all read latencies, which is measured by time between a read command is being accepted by the Controller till the first beat of read data is presented to the driver.

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