1. MAX® 10 External Memory Interface Overview
2. MAX® 10 External Memory Interface Architecture and Features
3. MAX® 10 External Memory Interface Design Considerations
4. MAX® 10 External Memory Interface Implementation Guides
5. UniPHY IP References for MAX® 10 Devices
6. MAX® 10 External Memory Interface User Guide Archives
7. Document Revision History for the MAX® 10 External Memory Interface User Guide
2.1. MAX® 10 I/O Banks for External Memory Interface
2.2. MAX® 10 DQ/DQS Groups
2.3. MAX® 10 External Memory Interfaces Maximum Width
2.4. MAX® 10 Memory Controller
2.5. MAX® 10 External Memory Read Datapath
2.6. MAX® 10 External Memory Write Datapath
2.7. MAX® 10 Address/Command Path
2.8. MAX® 10 PHY Clock (PHYCLK) Network
2.9. Phase Detector for VT Tracking
2.10. On-Chip Termination
2.11. Phase-Locked Loop
2.12. MAX® 10 Low Power Feature
2.8. MAX® 10 PHY Clock (PHYCLK) Network
The PHYCLK network is a dedicated high-speed and low skew balanced clock tree that provides better clock skew for external memory interface applications.
In MAX® 10 devices, only the top right PLL is routed to the PHYCLK tree. Therefore, the PHYCLK tree is available only for the I/O banks on the right side of the MAX® 10 10M16, 10M25, 10M40, and 10M50 devices.
Figure 7. I/O Banks for External Memory Interfaces This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.