MAX® 10 External Memory Interface User Guide

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ID 683087
Date 3/17/2025
Public
Document Table of Contents
Document Table of Contents x
1. MAX® 10 External Memory Interface Overview 2. MAX® 10 External Memory Interface Architecture and Features 3. MAX® 10 External Memory Interface Design Considerations 4. MAX® 10 External Memory Interface Implementation Guides 5. UniPHY IP References for MAX® 10 Devices 6. MAX® 10 External Memory Interface User Guide Archives 7. Document Revision History for the MAX® 10 External Memory Interface User Guide
1. MAX® 10 External Memory Interface Overview x
1.1. MAX® 10 External Memory Interface Support and Performance
2. MAX® 10 External Memory Interface Architecture and Features x
2.1. MAX® 10 I/O Banks for External Memory Interface 2.2. MAX® 10 DQ/DQS Groups 2.3. MAX® 10 External Memory Interfaces Maximum Width 2.4. MAX® 10 Memory Controller 2.5. MAX® 10 External Memory Read Datapath 2.6. MAX® 10 External Memory Write Datapath 2.7. MAX® 10 Address/Command Path 2.8. MAX® 10 PHY Clock (PHYCLK) Network 2.9. Phase Detector for VT Tracking 2.10. On-Chip Termination 2.11. Phase-Locked Loop 2.12. MAX® 10 Low Power Feature
2.5. MAX® 10 External Memory Read Datapath x
2.5.1. DDR Input Registers
2.6. MAX® 10 External Memory Write Datapath x
2.6.1. DDR Output Registers
3. MAX® 10 External Memory Interface Design Considerations x
3.1. MAX® 10 DDR2 and DDR3 Design Considerations 3.2. LPDDR2 Design Considerations 3.3. Guidelines: DDR3, DDR2, and LPDDR2 External Memory Interface I/O Limitation 3.4. Guidelines: Board Design Requirement for DDR2, DDR3, and LPDDR2 3.5. Guidelines: Reading the MAX® 10 Pin-Out Files
3.1. MAX® 10 DDR2 and DDR3 Design Considerations x
3.1.1. DDR2/DDR3 External Memory Interface Pins 3.1.2. DDR2/DDR3 Recommended Termination Schemes for MAX® 10 Devices
3.1.1. DDR2/DDR3 External Memory Interface Pins x
3.1.1.1. MAX® 10 Data and Data Clock (Data Strobe) Pins 3.1.1.2. Data Mask Pins 3.1.1.3. DDR2/DDR3 Error Correction Coding Pins 3.1.1.4. DDR2/DDR3 Address and Control/Command Pins 3.1.1.5. Memory Clock Pins
3.1.1.1. MAX® 10 Data and Data Clock (Data Strobe) Pins x
3.1.1.1.1. MAX® 10 I/O Bank DQ/DQS Support for DDR2/DDR3
3.2. LPDDR2 Design Considerations x
3.2.1. LPDDR2 External Memory Interface Pins 3.2.2. LPPDDR2 Power Supply Variation Constraint 3.2.3. LPDDR2 Recommended Termination Schemes for MAX® 10 Devices
3.2.1. LPDDR2 External Memory Interface Pins x
3.2.1.1. MAX® 10 Data and Data Clock (Data Strobe) Pins 3.2.1.2. Data Mask Pins 3.2.1.3. LPDDR2 Address and Control/Command Pins 3.2.1.4. Memory Clock Pins
3.2.1.1. MAX® 10 Data and Data Clock (Data Strobe) Pins x
3.2.1.1.1. MAX® 10 I/O Bank DQ/DQS Support for LPDDR2
4. MAX® 10 External Memory Interface Implementation Guides x
4.1. UniPHY IP Core 4.2. LPDDR2 External Memory Interface Implementation 4.3. DDR2 and DDR3 External Memory Interface Implementation
4.2. LPDDR2 External Memory Interface Implementation x
4.2.1. Supported LPDDR2 Topology
4.3. DDR2 and DDR3 External Memory Interface Implementation x
4.3.1. MAX® 10 Supported DDR2 or DDR3 Topology
5. UniPHY IP References for MAX® 10 Devices x
5.1. UniPHY Parameter Settings for MAX® 10
5.1. UniPHY Parameter Settings for MAX® 10 x
5.1.1. UniPHY Parameters—PHY Settings 5.1.2. UniPHY Parameters—Memory Parameters 5.1.3. UniPHY Parameters—Memory Timing 5.1.4. UniPHY Parameters—Board Settings 5.1.5. UniPHY Parameters—Controller Settings 5.1.6. UniPHY Parameters—Diagnostics
1. MAX® 10 External Memory Interface Overview
2. MAX® 10 External Memory Interface Architecture and Features
3. MAX® 10 External Memory Interface Design Considerations
4. MAX® 10 External Memory Interface Implementation Guides
5. UniPHY IP References for MAX® 10 Devices
6. MAX® 10 External Memory Interface User Guide Archives
7. Document Revision History for the MAX® 10 External Memory Interface User Guide

7. Document Revision History for the MAX® 10 External Memory Interface User Guide

Document Version Quartus® Prime Version Changes
2025.03.17 24.1
  • Added package B610 for the 10M40 and 10M50 devices.
  • Updated links to related information.
  • Updated document title.
2022.10.31 21.1
  • Updated the Memory Standards Supported by the Soft Memory Controller for MAX® 10 Devices table.
    • Removed contact information for –A6 speed grade devices.
    • Added note on automotive-grade devices do not support external memory interfaces.
2021.11.01 21.1 Removed –I6 speed grade from contact information in the Memory Standards Supported by the Soft Memory Controller for MAX® 10 Devices table. All OPNs for –I6 speed grade are available in the Quartus® Prime Standard Edition software version 21.1 onwards.
2021.04.01 16.1
  • Updated Table Termination Recommendations for Intel MAX 10 DDR2 Component:
    • Changed SSTL 18 I/O Standard for DQ/DQS, DM and Clock Signal Type.
    • Added FPGA - End Discrete Termination for Address and Command Signal Type.
    • Changed Memory-End Termination 1 for DM Signal Type.
    • Added Memory I/O Standard for DM Signal Type.
2020.10.15 16.1
  • Renamed the document as MAX® 10 External Memory Interface User Guide.
  • Updated MAX® 10 I/O Banks for External Memory Interface.
  • Updated for latest Altera branding standards.
Date Version Changes
February 2017 2017.02.21
  • Rebranded as Intel.
October 2016 2016.10.28
  • Updated Memory Standards Supported by the Soft Memory Controller for MAX 10 devices table.
May 2016 2016.05.02
  • Updated UniPHY IP core parameter settings for LPDDR2, DDR2 and DDR3.
  • Updated Supported Maximum External Memory Interface Width in MAX® 10 Device Packages table.
  • Added MAX® 10 External Memory Interface User Guide Archives table.
  • Updated DDR2, DDR3 and LPDDR2 can use only user I/O pins from banks 5 and 6 of MAX® 10 devices to generate address and control or command signals..
November 2015 2015.11.02
  • Added links to MAX® 10 DDR3 UniPHY IP core reference design.
  • Added topic that lists the maximum external memory interface widths supported for different MAX® 10 device packages.
  • Removed the topics about the IP catalog and parameter editor, generating IP cores, and the files generated by the IP core, and added a link to Introduction to Altera IP Cores.
  • Changed instances of Quartus II to Quartus Prime.
May 2015 2015.05.11 Added on board termination recommendation for DDR3 component.
May 2015 2015.05.04
  • Updated the footnote in the topic about external memory interface support and performance to specify that the default maximum frequency for LPDDR2 is 167 MHz.
  • Removed the F672 package from the 10M25 device.
  • Removed the note about contacting Altera for DDR3, DDR3L, DDR2, and LPDDR2 external memory interface support. The Quartus® Prime software supports these external memory interfaces from version 15.0.
  • Added a topic about the PHYCLK network.
  • Moved information about recommended LPDDR2 termination scheme into a new topic under LPDDR2 design considerations section. The information was previously in the topic about recommended DDR2/DDR3 termination schemes.
  • Updated the guidelines about board design requirement to improve clarity.
  • Updated and added related information links to relevant information.
  • Added a topic about the low power feature available from version 15.0 of the Quartus® Prime software.
  • Updated the topic about the phase detector to add a figure showing the VT tracking system overview.
December 2014 2014.12.15
  • Changed Altera MAX 10 EMIF IP core to UniPHY IP core.
  • Removed reference to DIMM in a footnote under the table that lists the termination recommendations for DDR2 component. The UniPHY IP core for MAX® 10 does not support DIMM.
  • Added a list of the MAX 10 memory controller features.
  • Added "Preliminary" tag to the table that lists the I/Os unavailable in certain MAX 10 packages while implementing DDR3 or LPDDR2 external memory interfaces.
  • Updated the board design requirement with additional guidelines.
  • Added information for the MAX 10 external memory interface UniPHY IP core. This addition includes the chapters about external memory interface implementation and IP core references.
  • Edited texts and added related information links to improve clarity.
September 2014 2014.09.22 Initial release.
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