MAX® 10 External Memory Interface User Guide

Download PDF
ID 683087
Date 3/17/2025
Public
Document Table of Contents
Document Table of Contents x
1. MAX® 10 External Memory Interface Overview 2. MAX® 10 External Memory Interface Architecture and Features 3. MAX® 10 External Memory Interface Design Considerations 4. MAX® 10 External Memory Interface Implementation Guides 5. UniPHY IP References for MAX® 10 Devices 6. MAX® 10 External Memory Interface User Guide Archives 7. Document Revision History for the MAX® 10 External Memory Interface User Guide
1. MAX® 10 External Memory Interface Overview x
1.1. MAX® 10 External Memory Interface Support and Performance
2. MAX® 10 External Memory Interface Architecture and Features x
2.1. MAX® 10 I/O Banks for External Memory Interface 2.2. MAX® 10 DQ/DQS Groups 2.3. MAX® 10 External Memory Interfaces Maximum Width 2.4. MAX® 10 Memory Controller 2.5. MAX® 10 External Memory Read Datapath 2.6. MAX® 10 External Memory Write Datapath 2.7. MAX® 10 Address/Command Path 2.8. MAX® 10 PHY Clock (PHYCLK) Network 2.9. Phase Detector for VT Tracking 2.10. On-Chip Termination 2.11. Phase-Locked Loop 2.12. MAX® 10 Low Power Feature
2.5. MAX® 10 External Memory Read Datapath x
2.5.1. DDR Input Registers
2.6. MAX® 10 External Memory Write Datapath x
2.6.1. DDR Output Registers
3. MAX® 10 External Memory Interface Design Considerations x
3.1. MAX® 10 DDR2 and DDR3 Design Considerations 3.2. LPDDR2 Design Considerations 3.3. Guidelines: DDR3, DDR2, and LPDDR2 External Memory Interface I/O Limitation 3.4. Guidelines: Board Design Requirement for DDR2, DDR3, and LPDDR2 3.5. Guidelines: Reading the MAX® 10 Pin-Out Files
3.1. MAX® 10 DDR2 and DDR3 Design Considerations x
3.1.1. DDR2/DDR3 External Memory Interface Pins 3.1.2. DDR2/DDR3 Recommended Termination Schemes for MAX® 10 Devices
3.1.1. DDR2/DDR3 External Memory Interface Pins x
3.1.1.1. MAX® 10 Data and Data Clock (Data Strobe) Pins 3.1.1.2. Data Mask Pins 3.1.1.3. DDR2/DDR3 Error Correction Coding Pins 3.1.1.4. DDR2/DDR3 Address and Control/Command Pins 3.1.1.5. Memory Clock Pins
3.1.1.1. MAX® 10 Data and Data Clock (Data Strobe) Pins x
3.1.1.1.1. MAX® 10 I/O Bank DQ/DQS Support for DDR2/DDR3
3.2. LPDDR2 Design Considerations x
3.2.1. LPDDR2 External Memory Interface Pins 3.2.2. LPPDDR2 Power Supply Variation Constraint 3.2.3. LPDDR2 Recommended Termination Schemes for MAX® 10 Devices
3.2.1. LPDDR2 External Memory Interface Pins x
3.2.1.1. MAX® 10 Data and Data Clock (Data Strobe) Pins 3.2.1.2. Data Mask Pins 3.2.1.3. LPDDR2 Address and Control/Command Pins 3.2.1.4. Memory Clock Pins
3.2.1.1. MAX® 10 Data and Data Clock (Data Strobe) Pins x
3.2.1.1.1. MAX® 10 I/O Bank DQ/DQS Support for LPDDR2
4. MAX® 10 External Memory Interface Implementation Guides x
4.1. UniPHY IP Core 4.2. LPDDR2 External Memory Interface Implementation 4.3. DDR2 and DDR3 External Memory Interface Implementation
4.2. LPDDR2 External Memory Interface Implementation x
4.2.1. Supported LPDDR2 Topology
4.3. DDR2 and DDR3 External Memory Interface Implementation x
4.3.1. MAX® 10 Supported DDR2 or DDR3 Topology
5. UniPHY IP References for MAX® 10 Devices x
5.1. UniPHY Parameter Settings for MAX® 10
5.1. UniPHY Parameter Settings for MAX® 10 x
5.1.1. UniPHY Parameters—PHY Settings 5.1.2. UniPHY Parameters—Memory Parameters 5.1.3. UniPHY Parameters—Memory Timing 5.1.4. UniPHY Parameters—Board Settings 5.1.5. UniPHY Parameters—Controller Settings 5.1.6. UniPHY Parameters—Diagnostics
1. MAX® 10 External Memory Interface Overview
2. MAX® 10 External Memory Interface Architecture and Features
3. MAX® 10 External Memory Interface Design Considerations
4. MAX® 10 External Memory Interface Implementation Guides
5. UniPHY IP References for MAX® 10 Devices
6. MAX® 10 External Memory Interface User Guide Archives
7. Document Revision History for the MAX® 10 External Memory Interface User Guide

3.3. Guidelines: DDR3, DDR2, and LPDDR2 External Memory Interface I/O Limitation

While implementing certain external memory interface standards, the number of I/O pins available is limited.
  • While implementing DDR2—you can assign 75 percent of the available I/O pins in I/O banks 5 and 6 for normal I/O operation. For the remaining 25 percent of the I/O pins available in I/O banks 5 and 6, you can assign them only as input pins.
  • While implementing DDR3 or LPDDR2—the I/O pins listed in the following table are not available for use. can generally use 75% of the total number of I/O pins available in I/O banks 5 and 6 for normal I/O operation. This restriction differs from device to device. In some device packages you can use all 100% of the I/Os. The Quartus® Prime software outputs an error message if the restriction rule affects the I/O usage per bank of the device.
Table 9.  Unavailable I/O Pins While Implementing DDR3 or LPDDR2 External Memory Interfaces in Certain Device Packages—Preliminary
Device Package
F256 U324 F484 B610 F672

10M16

N16

P16

R15

P15

R18

P18

E16

D16

U21

U22

M21

L22

F21

F20

E19

F18

—

—

10M25

N16

P16

—

U21

U22

M21

L22

F21

F20

E19

F18

F17

E17

—

—

10M40

10M50

N16

P16

—

U21

U22

M21

L22

F21

F20

E19

F18

F17

E17

BC40

BC42

AH42

AH41

AF43

AF44

AD36

AD35

E42

E41

R41

R42

N41

N42

B40

A40

W23

W24

U25

U24

T24

R25

R24

P25

K23

K24

J23

H23

G23

F23

G21

G22
Level Two Title