1. MAX® 10 External Memory Interface Overview
2. MAX® 10 External Memory Interface Architecture and Features
3. MAX® 10 External Memory Interface Design Considerations
4. MAX® 10 External Memory Interface Implementation Guides
5. UniPHY IP References for MAX® 10 Devices
6. MAX® 10 External Memory Interface User Guide Archives
7. Document Revision History for the MAX® 10 External Memory Interface User Guide
2.1. MAX® 10 I/O Banks for External Memory Interface
2.2. MAX® 10 DQ/DQS Groups
2.3. MAX® 10 External Memory Interfaces Maximum Width
2.4. MAX® 10 Memory Controller
2.5. MAX® 10 External Memory Read Datapath
2.6. MAX® 10 External Memory Write Datapath
2.7. MAX® 10 Address/Command Path
2.8. MAX® 10 PHY Clock (PHYCLK) Network
2.9. Phase Detector for VT Tracking
2.10. On-Chip Termination
2.11. Phase-Locked Loop
2.12. MAX® 10 Low Power Feature
2.6. MAX® 10 External Memory Write Datapath
For all DDR applications supported by MAX® 10 devices, the DQS strobe is sent to the external DRAM as center-aligned to the write DQ data.
The clock that clocks DDIO registers of the DQ output is phase-shifted –90º from the clock that drives the DDIO registers of the DQS strobe. This create a DQS strobe that is center-aligned to the DQ data.
The external memory write datapath is not calibrated.