External Memory Interface Handbook Volume 2: Design Guidelines

ID 683385
Date 5/08/2017
Document Table of Contents PHY or Core9.6.3.1. PHY or Core

Timing analysis of the PHY or core path includes the path from the last set of registers in the core to the first set of registers in the periphery (C2P), path from the last set of registers in the periphery to the first of registers in the core (P2C) and ECC related path if it is enabled.

As with 28 nm devices, core timing analysis excludes user logic timing to or from EMIF blocks. The EMIF IP provides a constrained clock (for example: ddr3_usr_clk) with which to clock customer logic. In 28 nm devices, pll_afi_clk serves this purpose

The PHY or core analyzes this path by calling the report_timing command in <variation_name>_report_timing.tcl and <variation_name>_report_timing_core.tcl.

Note: In version 14.1 and later, the Spatial Pessimism Removal slack values in the Core to Periphery and Periphery to Core tables are always equal to zero. This occurs because pessimism removal is integrated into the base timing analysis.

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