7.2.2. Qsys System Integration Tool Design Flow
You easily can add other components and quickly create a Qsys system. Qsys automatically generates HDL files that include all of the specified components and interconnections. In Qsys, you specify the connections you want. The HDL files are ready to be compiled by the Quartus Prime software to produce output files for programming an Intel® device. Qsys generates Verilog HDL simulation models for the IP cores that comprise your system.
The following figure shows a high level block diagram of an example Qsys system.
For more information about the Qsys system interconnect, refer to the Qsys Interconnect chapter in volume 1 of the Quartus Prime Handbook and to the Avalon Interface Specifications .
For more information about the Qsys tool and the Quartus Prime software, refer to the System Design with Qsys section in volume 1 of the Quartus Prime Handbook and to Quartus Prime Help.
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