External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

7.2.2.2. Completing the Qsys System

To complete the Qsys system, follow these steps:
  1. Add and parameterize any additional components.
  2. Connect the components using the Connection panel on the System Contents tab.
  3. In the Export column, enter the name of any connections that should be a top-level Qsys system port.
    Note: Ensure that the memory and oct interfaces are exported to the top-level Qsys system port. If these interfaces are already exported, take care not to accidentally rename or delete either of them in the Export column of the System Contents tab.
  4. Click Finish.
  5. Specify the File Name and click Save.
  6. When you are prompted to generate now, click Yes.
  7. Set Create HDL design files for synthesis to either Verilog or VHDL.
    Tip: If you want to do RTL simulation of your design, you should set Create simulation model to either Verilog or VHDL. Some RTL simulation-related files, including simulator-specific scripts, are generated only if you specify this parameter.
    Note: For Arria 10 External Memory Interface IP, the synthesis and simulation model files are identical. However, there are some differences in file types when generating for VHDL. For synthesis files, only the top-level wrapper is generated in VHDL; the other files are generated in System Verilog. For simulation files, all the files are generated as a Mentor-tagged encrypted IP for VHDL-only simulator support.
  8. Click Generate.
  9. When generation has completed, click Finish.
  10. If you are prompted to add the .qip file to the current Quartus Prime project, click Yes (If you want, you can turn on Automatically Add Quartus Prime IP Files to all projects).
    Tip: Always read the generated readme.txt file, because it contains information and guidelines specific to your configuration.

You can now simulate and compile your design. But before compilation, you must make approrriate pin assignments. You can create a virtual pin to avoid making specific pin assignments for top-level signals during simulation and not yet ready to map the design to hardware.

For information about the Quartus Prime software, including virtual pins and the IP Catalog and Qsys, refer to the Quartus Prime Help.

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