6. QDR II and QDR-IV SRAM Board Design Guidelines
The QDR II and QDR II+ SRAM Controller with UniPHY intellectual property (IP) enables you to implement QDR II and QDR II+ interfaces with Arria® II GX, Arria V, Stratix® III, Stratix IV, and Stratix V devices.
The following topics focus on the following key factors that affect signal integrity:
- I/O standards
- QDR II SRAM configurations
- Signal terminations
- Printed circuit board (PCB) layout guidelines
QDR II SRAM interface signals use one of the following JEDEC I/O signalling standards:
- HSTL-15—provides the advantages of lower power and lower emissions.
- HSTL-18—provides increased noise immunity with slightly greater output voltage swings.
To select the most appropriate standard for your interface, refer to the Arria II GX Devices Data Sheet: Electrical Characteristics chapter in the Arria II Device Handbook, Stratix III Device Datasheet: DC and Switching Characteristics chapter in the Stratix III Device Handbook, or the Stratix IV Device Datasheet DC and Switching Characteristics chapter in the Stratix IV Device Handbook.
Altera QDR II SRAM Controller with UniPHY IP defaults to HSTL 1.5 V Class I outputs and HSTL 1.5 V inputs.
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