6.7. QDR-IV Layout Approach
The following flowchart illustrates the recommended process to follow during the design phase, to determine timing margin and make iterative improvements to your design.
For more detailed simulation guidance for Arria 10, refer to the wiki: http://www.alterawiki.com/wiki/Arria_10_EMIF_Simulation_Guidance
For information on intersymbol interference and crosstalk, refer to the wiki: http://www.alterawiki.com/wiki/Arria_10_EMIF_Simulation_Guidance
For information on calculating board skew parameters, refer to
If you know the absolute delays for all the memory related traces, the interactive Board Skew Parameter Tool can help you calculate the necessary parameters.
Memory Timing Parameters
You can find the memory timing parameters to enter in the parameter editor, in your memory vendor's datasheet.
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