External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

6.8. QDR-IV Layout Guidelines

Observe the following layout guidelines for your QDR-IV interface. These guidelines apply for all device families that support QDR-IV, including Arria 10 and Stratix 10.
Parameter Guidelines
General Routing
  • If you must route signals of the same net group on different layers with the same impedance characteristic, simulate your worst case PCB trace tolerances to determine actual propagation delay differences. Typical layer-to-layer trace delay variations are on the order of 15 ps/inch.
  • Avoid T-junctions greater than 150 ps.
  • Match all signals within a given DQ group with a maximum skew of ±10 ps and route on the same layer.
Clock Routing
  • Route clocks on inner layers with outer-layer run lengths held to less than 150 ps.
  • Clock signals should maintain a 10-mil (0.254 mm) spacing from other nets.
  • Clocks should maintain a length-matching between clock pairs of ±5 ps.
  • Differential clocks should maintain a length-matching between P and N signals of ±2 ps.
  • Space between different clock pairs should be at least three times the space between the traces of a differential pair.
Address and Command Routing
  • - To minimize crosstalk, route address, bank address, and command signals on a different layer than the data signals.
  • Do not route the differential clock signals close to the address signals.
  • Keep the distance from the pin on the QDR-IV component to the stub termination resistor (VTT) to less than 50 ps for the address/command signal group.
  • - Route the mem_ck (CK/CK#) clocks and set as the target trace propagation delays for the address/command signal group. Match the CK/CK# clock to within ±50 ps of all the DK/DK# clocks for both ports.
  • - Route the address/control signal group ideally on the same layer as the mem_ck (CK/CK#) clocks, to within ±20 ps skew of the mem_ck (CK/CK#) traces.
Data Signals
  • For port B only: Swap the polarity of the QKB and QKB# signals with respect to the polarity of the differential buffer inputs on the FPGA. Connect the positive leg of the differential input buffer on the FPGA to QDR-IV QKB# (negative) pin and vice-versa. Note that the port names at the top-level of the IP already reflect this swap (that is, mem_qkb is assigned to the negative buffer leg, and mem_qkb_n is assigned to the positive buffer leg).
  • For each port, route the DK/DK# write clock and QK/QK# read clock associated with a DQ group on the same PCB layer. Match these clock pairs to within ±5 ps.
  • For each port, set the DK/DK# or QK/QK# clock as the target trace propagation delay for the associated data signals (DQ).
  • For each port, route the data (DQ) signals for the DQ group ideally on the same layer as the associated QK/QK# and DK/DK# clocks to within ±10 ps skew of the target clock.
Maximum Trace Length
  • Keep the maximum trace length of all signals from the FPGA to the QDR-IV components to 600 ps.
Spacing Guidelines
  • Avoid routing two signal layers next to each other. Always make sure that the signals related to memory interface are routed between appropriate GND or power layers.
  • For Data and Data Strobe traces: Maintain at least 3H spacing between the edges (air-gap) of these traces, where H is the vertical distance to the closest return path for that particular trace.
  • For Address/Command/Control traces: Maintain at least 3H spacing between the edges (air-gap) of these traces, where H is the vertical distance to the closest return path for that particular trace.
  • For Clock (mem_CK) traces: Maintain at least 5H spacing between two clock pair or a clock pair and any other memory interface trace, where H is the vertical distance to the closest return path for that particular trace.

Trace Matching Guidance

The following layout approach is recommended, based on the preceding guidelines:

  1. For port B only: Swap the polarity of the QKB and QKB# signals with respect to the polarity of the differential buffer inputs on the FPGA. Connect the positive leg of the differential input buffer on the FPGA to QDR-IV QKB# (negative) pin and vice-versa. Note that the port names at the top-level of the IP already reflect this swap (that is, mem_qkb is assigned to the negative buffer leg, and mem_qkb_n is assigned to the positive buffer leg).
  2. For each port, set the DK/DK# or QK/QK# clock as the target trace propagation delay for the associated data signals (DQ).
  3. For each port, route the data (DQ) signals for the DQ group ideally on the same layer as the associated QK/QK# and DK/DK# clocks to within ±10 ps skew of the target clock.
  4. Route the mem_ck (CK/CK#) clocks and set as the target trace propagation delays for the address/command signal group. Match the CK/CK# clock to within ±50 ps of all the DK/DK# clocks for both ports.
  5. Route theaddress/control signal group ideally on the same layer as the mem_ck (CK/CK#) clocks, to within ±10 ps skew of the mem_ck (CK/CK#) traces.

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